U. Glaeser

PD-SOI Application to High-Performance MPU
An example of a prototype LSI that employs PD-SOI technology and which was presented at the latest
ISSCC is shown in Table 2.4. The year 1999 will be remembered as far as application of SOI to a highperformance
MPUs is concerned. In an independently organized session at ISSCC that focused on SOI
technology, IBM reported a 32-bit Power PC (chip size of 49 mm 2 ) that employs 0.25 µm PD-SOI
technology [15] and a 64-bit Power PC (chip size of 139 mm 2 ) that employs 0.2 µm PD-SOI technology
[16]. Samsung reported a 64-bit ALPHA microprocessor (chip size of 209 mm 2 ) that employs 0.25 µm
FD-SOI technology [17]. According to IBM, the SOI-MPU attained performance that was 20–35% higher
than an MPU fabricated using an ordinary bulk Si substrate. Furthermore, in the year 2000, IBM reported
the performance of a 64-bit Power PC microprocessor that was scaled down from 0.22 µm to 0.18 µm,
confirming a 20% increase in performance [18]. In this way, the scenario that increased performance
could be attained for SOI technology through finer design scales in the same way it can be done for bulk
Si devices was first established. IBM is attracting attention by applying these high-performance SOI-
MPUs to middle-range commercial products, such as servers for e-business etc. and shipping them to
market as examples of the commercialization of SOI technology [19]. Also, many manufacturers that are
developing high-performance MPUs have recently begun programs for developing SOI-MPU. Currently,
PD-SOI technology is becoming the mainstream in the high-performance MPU. The characteristics of
PD-SOI and FD-SOI are compared in Table 2.5. In the high-performance MPU, improvement of transistor
performance through aggressive increase in integration scale is an essential requirement, and PD-
SOI devices have the merit that the extremely fine device design scenario and process technology that
have been developed for bulk Si devices can be used without modification. Also, as described previously,
because the PD-SOI can have a thicker body region than the FD-SOI (about 100 nm), those devices have
the advantage of a greater fabrication margin in the contact forming process and the process for lowering
the parasitic resistance of the SOI layer. On the other hand, the PD-SOI devices exhibit a striking floating
© 2002 by CRC Press LLC
TABLE 2.4 PD-SOI Activities in ISSCC
LSIs Gate Length Performance VDD Company Year
Logic 0.3 µm 200 MHz 0.5 V Toshiba ’96
16 b Multiplier 0.18 µm 380 ns 1.5 V Intel ’01
ALU 0.08 µm 1 ns 1.3 V Fujitsu ’01
32 b Adder
DRAM
16 Mb 0.5 µm 46 ns 1 V Mitsubishi ’97
Microprocessor
32 b Power PC 0.25 µm 580 MHz 2 V IBM ’99
64 b Power PC 0.2 µm 550 MHz 1.8 V IBM ’99
64 b Power PC 0.18 µm 660 MHz 1.5 V IBM ’00
64 b PA-RISC 0.18 µm 1 GHz 1.5 V HP ’01
TABLE 2.5 FD vs. PD
FD PD
Manufacturability +
Kink effect +
Body contact +
V th control +
SCE (scaling ability) +
Parasitic resistivity +
Breakdown voltage +
Subthreshold slope +
Pass gate leakage +
History dependence +