U. Glaeser

of the prediction. Until only several years ago, most of the people did not believe the possibility of gate
SiO 2 thinning below 3 nm because of the direct-tunnelling leakage current, and until only 2 years ago,
many people are sceptical about the use of sub-2 nm gate SiO 2 because of the TDDB concern.
However, even excellent characteristics of MOSFETs with high reliability was confirmed, total gate leakage
current in the entire LSI chip would become the limiting factor. It should be noted that 10 A/cm 2 gate
leakage current flows across the gate SiO 2 at t ox = 1.2 nm and 100 A/cm 2 leakage current flows at t ox = 1.0 nm.
However, AMD has claimed that 1.2 nm gate SiO 2 (actually oxynitrided) can be used for high end MPUs
[26]. Furthermore, Intel has announced that total-chip gate leakage current of even 100 A/cm 2 is allowable
for their MPUs [14], and that even 0.8 nm gate SiO 2 (actually oxynitrided) can be used for product in
2005 [15].
Total gate leakage current could be minimized by providing plural gate oxide thicknesses in a chip,
and by limiting the number of the ultra-thin transistors; however, in any case, such high gate leakage
current density is a big burden for mobile devices, in which reduction of standby power consumption
is critically important. In the cellular phone application, even the leakage current at t ox = 2.5 nm would
be a concern. Thus, development of high dielectric constant (or high-k) gate insulator with small gate
leakage current is strongly demanded; however, intensive study and development of the high-k gate
dielectrics have started only a few years ago, and it is expected that we have to wait at least another few
years until the high-k insulator becomes mature for use of the production.
The necessary conditions for the dielectrics are as follows [27]: (i) the dielectrics remain in the solidphase
at the process temperature of up to about 1000 K, (ii) the dielectrics are not radio-active, (iii) the
dielectrics are chemically stable at the Si interface at high process temperature. This means that no barrier
film is necessary between the Si and the dielectrics. Considering the conditions, white columns in the
periodic law of the elements shown in Fig. 1.20 remained as metals whose oxide could be used as the
high-k gate insulators [27]. It should be noted that Ta 2O 5 is now regarded as not very much suitable for
use as the gate insulator of MOSFET from this point of view.
Figure 1.21 shows the statistics of high-k dielectrics—excluding Si 3N 4—and its formation method
published recently [28–43]. In most of the cases, 0.8–2.0 nm capacitance equivalent thicknesses to SiO 2
(CET) were tested for the gate insulator of MOS diodes and MOSFETs and leakage current of several
orders of magnitude lower value than that of SiO 2 film was confirmed. Also, high TDDB reliability than
that of the SiO 2 case was reported.
H
FIGURE 1.20 Metal oxide gate insulators reported since Dec. 1998 [27].
© 2002 by CRC Press LLC
Li Be
Na
K
Mg
React with Si.
Other failed reactions.
Reported since Dec. 1999.
(MRS, IEDM, ECS, VLSI)
B C N O F Ne
Ca Sc Ti
V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr
Rh Sr Y Zr Nb Mo Tc Ru Rb Pd Ag Cd In Sn Sb Te I Xe
Cs Ba Hf Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn
Fr Ra Rf Ha Sg Ns Hs Mt
He
Al Si P S Cl Ar
La Ce Pr Nd Pm Sm Eu Gd Tb Dy Ho Er Tm Yb Lu
Ac Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr
Plotted on the material given by J. R. Hauser
at IEDM Short Course on Sub-100 nm CMOS (1999)