U. Glaeser

FIGURE 39.24 AltiVec’s VSUMMBM instruction: only one-fourth of the instruction is shown. Each box represents
a byte. This process is carried out for each 32-bit word in the 128-bit source registers.
amounts allowed are by one, two, or three bits, and the arithmetic is performed with signed saturation,
for 16-bit subwords.
Vector Multiplication
So far, this chapter has examined relatively simple packed multiply instructions. These instructions all
take about the same latency as a single multiply instruction, which is typically 3–4 cycles compared to
an add instruction normalized to one cycle latency. For better or worse, some multimedia ISAs have included
very complex, multiple-cycle operations. For example, AltiVec has a packed vector multiply and
accumulate instruction, using three 128-bit packed source operands and a 128-bit target register (see
Fig. 39.24). First, all the pairs of bytes within a 32-bit subword in two of the source registers are multiplied
in parallel and 16-bit products are generated. Then, four 16-bit products are added to each other to
generate a “sum of products” for every 32 bits. A 32-bit subword from the third source register is added
to this “sum of products.” The resulting sum is placed in the corresponding 32-bit subword field of the
target register. This process is repeated for each of the four 32-bit subwords. This is a total of sixteen 8-bit
integer multiplies, twelve 16-bit additions, and four 32-bit additions, using four 128-bit registers, in a
single VSUMMBM instruction. This can perform a 4 × 4 matrix times a 4 × 1 vector multiplication, where
each element is a byte, in a single instruction, but this single complex instruction takes many cycles of
latency. While a multiplication of a 4 × 4 matrix with a 4 × 1 vector is a very frequent operation in
graphics geometry processing, the precision required is usually that of 32-bit single-precision floatingpoint
numbers, not 8-bit integers. Whether the complexity of such a compound VSUMMBM instruction
is justified depends on the frequency of such 4 × 4 matrix-vector multiplications of bytes. Table 39.4
summarizes the packed integer multiplication instructions described.
© 2002 by CRC Press LLC