U. Glaeser

automata (GCA); an example of traffic system simulation is described—digital circuits and forest fire
development are further systems, which have suitable characteristics [13].
Petri net models are also used extensively in simulation studies; as with cellular automata, there is
abundant low level parallelism to be exploited—the firability of each transition can be evaluated simultaneously.
Petri net models are based on simple units—places and transitions. It is possible to create generic
models in VHDL for these units [14], paving the way to automatic generation of VHDL code from natural
visual representation of Petri nets, which can be compiled and downloaded to suitable hardware. A single
Achilles stack is able to accommodate a model containing of the order of 200 transitions [14].
Reconfigurable Processors vs. Commodity Processors
Any special purpose hardware has to compete with the rapid increase in performance of commodity
processors. Despite the relative inefficiency of a general-purpose processor for many applications, if the
special purpose hardware only provides a speedup of, say 2, then Moore’s Law will ensure that the advantage
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of the special purpose hardware is lost in a year. When assessing whether an application will benefit
from use of a reconfigurable processor, one has to keep the following points in mind.
Raw Performance
The raw performance of FPGA-based solutions will always lag behind that of commodity processors.
This is superficially reflected in maximum clock speeds: an FPGA’s maximum clock speed will typically
be one-third or less of that of a commodity processor at the same point in time. This is inevitable and
will continue: the reconfiguration circuitry loads a circuit and requires space, increasing its propagation
delay and reducing the maximum clock speed.
Parallelism
Thus, to realize a benefit from a reconfigurable system, the application must have a considerable degree
of inherent parallelism which can be used effectively.
The parallelism may be exploited simply by deploying multiple processing blocks—each processing a
separate data element at the same time—followed by some “aggregation” circuitry, which reduces results
from the individual processing blocks in some way.
Long Pipelines
Alternatively, a long pipeline may be employed in which the same data element transits multiple processing
blocks in successive clock cycles. This approach trades latency for throughput: it may take many
cycles—the latency—for the first result to appear, but after that new processed data are available on
each clock cycle giving high throughput. Many signal processing tasks can effectively use long pipelines.
Memory
FPGA devices do not provide large amounts of memory efficiently: recent devices (e.g., Altera’s APEX
20K devices [2]) do attempt to address this deficiency and provide significant dedicated memory resources;
however, the total number of memory bits remains relatively small and is insufficient to support applications
which require large amounts of randomly accessible data. This means that, although preprocessing
an image which is available as a pixel stream from a camera for edge detection is feasible, subsequent
processing of the image in order to segment it is considerably more difficult. In the first case, to apply a
3 × 3 mask to the pixel stream, only two preceding rows of the image need be stored. The application of
the 3 × 3 mask requires a maximum of nine basic multiply-accumulate operations. Thus, it can be effectively
handled in a 9-stage pipeline—easily allowing an edge-detected image to be produced at the same rate
as the original image is streamed into the FPGA (allowing for an 8-pixel clock latency before the first
result is available). In the second, the whole image needs to be stored and be available for random access.
Although an FPGA with auxillary memory might handle this task, it is less likely to offer a significant
advantage over a general-purpose processor.
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The author has (somewhat arbitrarily) shortened the “break-even” point from the 18 months of Moore’s Law,
because the extra cost of additional hardware needs to be factored in versus using cheap commodity hardware.
© 2002 by CRC Press LLC