U. Glaeser

FIGURE 2.4
circuit.
This is the basic principle behind the realization of CMOS logic circuits. A CMOS logic gate consists of
an NMOS pull-down network and a complementary PMOS pull-up network. The NMOS pull-down
network is connected between the output and the ground. The PMOS pull-up network is connected
between the output and the power supply,
© 2002 by CRC Press LLC
The general structure of a CMOS logic
FIGURE 2.5 A CMOS inverter: logic symbol, CMOS realization, and the switch level equivalent circuit when the
input is equal to 0 and 1.
V
DD
. The inputs go to both the networks. This is schematically
illustrated in Fig. 2.4. The number of transistors in each network is equal to the number of inputs. The
NMOS pull-down network can be designed using the series and parallel switches illustrated in Fig. 2.3.
The PMOS pull-up network is designed as a dual of NMOS pull-down network. That is, parallel components
in NMOS network translate into series components in the PMOS network, and series components
in NMOS network translate into parallel components in PMOS network. This procedure is elaborated by
design examples later in this section.
For a given combination of inputs, when the output is a logic 0, the NMOS network provides a closed
path between the output and ground, thereby pulling the output down to ground (logic 0). This is the
reason for the name NMOS pull-down network. When the output is a logic 1, for a given combination
of inputs, the PMOS network provides a closed path between the output and VDD,
thereby pulling the
output up to VDD
(logic 1). This is the reason for the name PMOS pull-up network. For CMOS logic gates
for both the outputs (0 and 1), we get strong signals at the output. If the output is a logic high, we get a
strong 1 since the output gets connected to VDD
through the PMOS pull-up network, and if the output is
a logic low, we get a strong 0 since the output gets connected to VSS
through the NMOS pull-down network.
It should be clearly noticed that only one of the networks remains closed at a given time for any combination
of the inputs. Therefore, at steady state no dc path exists between VDD
and ground and hence no
power dissipation. This is the primary reason for the inherent low power dissipation of CMOS VLSI circuits.
We now illustrate the CMOS realization of inverters, NAND and NOR logic circuits. An inverter is
the simplest possible of all the logic gates. An inverter can be constructed by using a PMOS and an NMOS
transistor. Figure 2.5 shows the logic symbol, CMOS realization and switch level equivalent circuits of
the inverter for both a 0 input and a 1 input. When the input is 0, the NMOS transistor is open (or OFF)
and the PMOS transistor is closed (or ON). Since the P switch is closed, the output is pulled high to VDD
(logic 1). When the input is 1, the PMOS transistor is OFF and the NMOS transistor is ON, and the
output is pulled down to ground (logic 0), which is the expected result of an inverter circuit.