U. Glaeser

Kevin J. Nowka
IBM Austin Research Laboratory
© 2002 by CRC Press LLC
13
Issues in High-Frequency
Processor Design
13.1 The Processor Implementation Performance
Food-Chain
Placement and Routing: Distance and Wire Loads Are
Performance • Fast Wires and Fast Devices: Gain Is
Performance • Gate Design: Boolean Efficiency Is
Performance
13.2 Noise, Robustness, and Reliability
13.3 Logic Design Implications
13.4 Variability and Uncertainty
13.5 Summary
Successful design of high-frequency processors is predominantly the act of balancing two competing
forces: striving to exploit the most advanced technology, circuits, logic implementations, and system
organization; and the necessity to encapsulate the resulting complexity so as to make the task tractable.
This chapter addresses some of the compelling issues in high-frequency processor design, both in taking
advantage of the technology and circuits and avoiding the pitfalls.
Advances in silicon technology, circuit design techniques, physical design tools, processor organization
and architecture, and market demand are producing frequency improvement in high-performance microprocessors.
Figure 13.1 shows the anticipated global and local clock frequency of high-performance
microprocessors from the SIA International Technology Roadmap for Semiconductors. 1,2 Because silicon
technology continuously advances, it is necessary to either define high frequency at each time or define
it in a technology-independent manner. For the remainder of this chapter, high frequency will be defined
in terms of the technology-independent unit of fanout-of-4 (FO4) inverter delay. 3 Figure 13.2 presents
the expected global clock frequency in terms of the ITRS gate delays. 1,2 From this figure, it is apparent that
the local cycle time of high-performance microprocessors is expected to shrink by about a factor of two
in number of gate delays. The ITRS gate delay is approximately a fanout-1 inverter delay, which is roughly
a fixed fraction of one FO4. This cycle time improvement must be provided by improvements in the use
of devices and interconnect, circuits, arithmetic, and organizational changes.
This chapter will concentrate on high-frequency designs, currently defined as less than 18 FO4 inverter
delays for a 64-bit processor and 16 FO4 for a 32-bit processor. These break-points are chosen because
(1) representative designs have been developed, which satisfy these criteria, 4–7 (2) they are sufficiently
aggressive to demonstrate the difficulties in achieving high-frequency designs, and (3) they fall firmly
within the expected targets of the high-performance microprocessor roadmaps.
In the remainder of this chapter, issues related to the design of processors for these high-frequency
targets will be described. The ultimate dependence of the achievable cycle times on interconnect efficiency
on low latency circuits will be discussed, and potential problems will be described.