U. Glaeser

tools, the + 1 operation is a special case and it generates a smaller and faster increment circuit instead of
an adder. Following the CASE statement, the next section of code in each model generates the shift
operation and selects the shifted or non-shifted value with a 16-bit wide 2-to-1 multiplexer generated
by the IF statement. The result is then loaded into a 16-bit register. All signal assignments following the
VHDL WAIT or second Verilog ALWAYS block will be registered since they are a function of the clock
signal. In VHDL WAIT UNTIL RISING_EDGE(CLOCK) and in Verilog ALWAYS@(POSEDGE CLOCK)
instructs the synthesis tool to use positive edge-triggered D flip-flops to build the register. A few additional
Library and Use statements at the start of each VHDL model will be required in some VHDL tools to
define the IEEE standard logic type. For additional information on writing HDLs for logic synthesis
models, select an HDL reference text that includes example models intended for synthesis and not just
simulation [6–15].
Behavioral synthesis tools using VHDL and Verilog behavioral level models have also been developed.
Unlike RTL level models, behavioral level models do not specify states and the required sequence of
register transfers. Behavioral compilers automatically design the state machine, allocate and schedule the
logic and ALU operations, and register transfers subject to a set of constraints. These constraints are
typically the number of clock cycles required to obtain selected signals [16]. By modifying these constraints,
different design architectures and alternatives are automatically generated.
Newer system-level synthesis languages based on C and Java have also been recently developed but are
not currently in widespread use in industry. These languages more closely resemble a traditional program
that describes an algorithm without specifying register transfers at the clock level. Many of these tools
output a VHDL or Verilog RTL description as an intermediate step. Some new tools are also appearing that
automatically generate FPGA designs using other popular engineering design software such as MATLAB.
CAD tools for synthesis are available from the both the device manufacturers and third party vendors.
Third party logic synthesis tools often provide higher performance and offer the advantage of supporting
devices from several manufacturers. This makes it easier to retarget a design to a device from a different
chip manufacturer. Following logic synthesis, many of the third party tools use the device manufacturer’s
standard place and route tools. Interfacing, configuring, and maintaining a design flow that uses various
CAD tools provided by different vendors can be a complex task. Several academically oriented texts
contain additional details on the logic synthesis and optimization algorithms used internally in FPGA
CAD tools [17–20].
IP Cores for FPGAs
Intellectual property (IP) cores are widely used in large designs. IP cores are commercial hardware designs
that provide frequently used operations. These previously developed designs are available as commercially
licensed products from both FPGA manufacturers and third party IP vendors. FPGA manufacturers
typically provide several basic hardware functions bundled with their devices and CAD tools. These
functions will work on their devices only. They include RAM, ROM, CAM, FIFO buffers, shift registers,
addition, multiply, and divide hardware. A few of these device specific functions may be used by an HDL
synthesis tool automatically, some must be called as library functions from an HDL, or entered using
special symbols in a schematic. Explicitly invoking these FPGA vendor specific functions in HDL function
calls or using the special symbols in a schematic may improve performance, but it also makes it more
difficult to retarget a design to a different FPGA manufacturer.
Commercial third-party IP cores include microprocessors, communications controllers, standard bus
interfaces, and DSP functions. IP cores can reduce development time and help promote design reuse by
providing widely used hardware functions in complex hierarchical designs. For FPGAs, commercial IP
cores are typically a synthesizable HDL model or in a few cases a custom VLSI layout that is added to
the FPGA. Several large FPGA families are now available with multipliers or RISC microprocessor IP
cores [21]. FPGAs with RISC microprocessors have additional support tools such as C compilers and
design tools to configure the processor and I/O systems. In the near future, it is likely that a small operating
system kernel will also be supplied with these tools. These new devices are a hybrid that contains both
ASIC and FPGA features.
© 2002 by CRC Press LLC