U. Glaeser

FIGURE 10.45 Max-timing diagrams for nonoverlapping dual-phase, latch-based design.
a transparent period is created between adjacent pipeline stages, eliminating the possibility of races.
Notice that the insertion of a complementary latch, while driven by the need to slow fast signals, ends
up slowing down max paths also. Although, in principle, a dual-phase design is race free, clock skew
may still cause min-timing problems. The clock phases may be nonoverlapping or fully complementary.
The timing requirement of a nonoverlapping dual-phase, latch-based design is discussed below. A dualphase
complementary design is treated later on as a special case.
Max-timing
Because a signal in a max path has to go through two latches in a dual-phase latch-based design the Dto-Q
latency of the latch is paid twice in the cycle. This is shown in the timing diagram of Fig. 10.45.
The max-timing constraint in a dual-phase design is therefore given by
© 2002 by CRC Press LLC
CK A
CK B
D 1
Q 1
D 1 ′
Q 1′
D 1 ″
Q 1 ″
T ON
Transparent
Opaque Transparent
TSETUP THOLD TSETUP THOLD T DQ
T MAX
(10.17)
The above equation remains still valid under the presence of clock skew. By comparing it against Eq.
(10.2), it is evident that as a result of the middle latch insertion the pipeline overhead (2T DQ) becomes
twice as large as in the single-latch design.
Time Borrowing
Time borrowing does not get affected either by the insertion of the complementary latch. Maximum
time borrowing is still given by Eq. (10.9), or by Eq. (10.14) in the presence of clock skew.
Min-timing
Min-timing is the most affected by the introduction of the complementary latch. As pointed out earlier, the
complementary latch insertion is a solution to relax the min-timing requirement of a latch-based design.
Figure 10.46 provides a timing diagram illustrating how a dual-latch design prevents races. Clock CKA and CKB are nonoverlapping clock phases, with TNOV being the nonoverlapping time. With reference to
Fig. 10.44, the input D2 to the sending latch is assumed to be blocked. After a CK-to-Q and a Tmin delay,
signal D′ 2 arrives at the middle latch while it is still opaque. Therefore, D′ 2 gets blocked until CKB transitions and the latch becomes transparent. A CK-to-Q delay later, signal Q′ 2 transitions. If the
nonoverlapping time is long enough, the Q′ 2
transition satisfies the hold time of the sending latch. The
same phenomenon happens in the second half of the stage.
T CYC
Opaque
T DQ
Tmax < TCYC – 2TDQ T MAX ′