U. Glaeser

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Some Basic Rules There are some basic rules that can be proposed to reduce power consumption at system and architecture levels: • Reduction of the number N of operations to execute a given task. • Sequencing that is too high always consumes more than the same functions executed in parallel. • Obviously, parallel architectures provide better clock per instruction (CPI), as well as pipelined and RISC architectures. • The lowest Vdd for the specific application has to be chosen. • The goal is to design a chip that just fits to the speed requirements [10]. The main point is to think about systems, with power consumption reduction in mind. According to the mentioned basic rules, how to design a SoC that uses parallelism, at the right supply voltage, while minimizing the steps to perform a given operation or task. The choice of a given processor or a random logic block is also very important. A processor results in a quite high sequencing while a random logic block works more in parallel for a same specific task. The processor type has to be chosen according to the work to be performed; if 16-bit data are to be used, it is not a good idea to choose a less expensive 8-bit controller and to work in double precision (high sequencing). CAD Tools Each specialized processor embedded in a SoC will be programmed in C and will execute after compilation its own code. Low-power software techniques have to be applied to each piece of software, including pruning, inlining, loop unrolling, and so on. For reconfigurable processor cores, retargetable compilers have to be available. The parallel execution of all these task have to be synchronized through communication links between processors and peripherals. It results that the co-simulation development tools have to deal with several pieces of software running on different processors and communicating between each other. Such a tool has to provide a high-level power estimation tool to check which are the power hungry processors, memories or peripherals as well as the power hungry software routines or loops [11]. Such a tool is far from being commercially available. Embedded low-power software emerges as a key design problem. The software content of SoC will increase as well as the cost of its development. Generally speaking, the available CAD tools for SoC chips have been designed for robust and reliable synchronous designs. It means that even gated clocks, low © 2002 by CRC Press LLC V dd , several V dd , are not or not yet supported, and that asynchronous and adiabatic will not be supported in the near future. It is a major problem, because CAD tools are far behind (10 years) the 2000 year requirements. Furthermore, little money is invested in CAD tools. It could be a stopper for some low-power methods. One can conclude that if power can be saved at a high level (factor 10 to 100 or more!) while using conventional CAD tools, it could be the way to go; however, power conscious SoC designers are required [12]. 18.3 Large Power Reduction at High Level As mentioned previously, a large part of the power can be saved at high level. Factors of 10 to 100 or more are possible; however, it means that the resulting system could be quite different, with less functionality or less programmability. The choice among various systems is strongly application dependent. One has to think about systems and low power to ask good questions of the customers and to get reasonable answers. Power estimation at high level is a very useful tool to verify the estimated total power consumption. Before starting a design for a customer, it is mandatory to think about the system and what is the goal about performances and power consumption. Several examples will be provided because this way of thinking is application dependent.
RF Devices An FM radio can be designed with an analog FM receiver as well as with analog and digital (random logic) demodulations, but a software radio has also been proposed. Such a system converts the FM signal directly into digital with very high-speed ADCs and does the demodulation work with a microprocessor. Such a solution is interesting as the same hardware can be used for any radio, but one can be convinced that a very high-speed ADC is a very consuming block, as well as a microprocessor that has to perform the demodulation (16-bit ADC can consume 1–10 W at 2.2 GHz [13]). In [13], some examples are provided for a digital baseband processor, achieving 1500 mW if implemented with a DSP processor and only 10 mW if implemented with a direct mapped ASIC. The latter case provides a factor of 150 in power reduction. The transmission of data from one location to another by RF link is more and more power consuming if the distance between the two points is increased. The power (although proportional to the distance at square in ideal case) is practically proportional to the distance at power 3 or even power 4 due to noise, interferences, and other problems. If three stations are inserted between the mentioned points, and assuming a power of 4, the power can be reduced by a factor 64. Low-Power Software Quite a large number of low-power techniques have been proposed for hardware, but relatively fewer for software. Hardware designers are today at least conscious that power reduction of SoCs is required for most applications. However, it seems that it is not the case for software people. Furthermore, a large part of the power consumption can be saved while modifying the application software. For embedded applications, it is quite often the case that an industrial existing C code has to be used to design an application (for instance, MPEG, JPEG). The methodology consists in improving the industrial C code by 1. pruning, some parts are removed. 2. clear separation of (a) the control code, (b) the loops, and (c) the arithmetic operations. Several techniques can be used to optimize the loops. In some applications, the application is 90% of the time running in loops. Three techniques can be used efficiently, such as loop fusion (loops executed in sequence with the same indices can be merged), loop tiling (to avoid fetching all the operands from the data cache for each loop iteration, so some data used by the previous iteration can be reused for the next iteration), and loop unrolling. To unroll a loop is to repeat the loop body N times if there are N iterations of the loop. The code size is increased, but the number of executed instructions is reduced, as the loop counter (initialization, incrementation, and comparison) is removed. A small loop executed eight times, for instance an 8 × 8 multiplication, results in at least 40 executed instructions, while the loop counter has to be incremented and tested. If the loop is unrolled, the code size is larger, but the number of executed instructions is reduced to about 24 (Fig. 18.2). This example illustrates a general rule: less sequencing in the software at the price of more hardware, i.e., more instructions in the program memory. Table 18.1 also shows that a linear routine (without loops) is executed with fewer instructions than a looped routine at the price of more instructions in the program. © 2002 by CRC Press LLC TABLE 18.1 Number of Instructions in the Code as well as the Number of Executed Instructions for an N × N Multiplication with a 2 × N Result Number of Instructions 8-bit Multiply Linear CoolRISC 88 in the Code 30 CoolRISC 88 Executed 30 PIC 16C5× in the Code 35 PIC 16C5× Executed 37 8-bit multiply looped 14 56 16 71 16-bit multiply linear 127 127 240 233 16-bit multiply looped 31 170 33 333
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© 2002 by CRC Press LLC
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© 2002 by CRC Press LLC Fernanda p
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Locating Your Topic Several avenues
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Krste Asanovic Massachusetts Instit
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7 8 9 Architectures for Low Power P
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SECTION VII Communications and Netw
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45 Testing of Synchronous Sequentia
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Hiroshi Iwai Tokyo Institute of Tec
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FIGURE 1.2 FIGURE 1.3 © 2002 by CR
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1.2 Downsizing below 0.1 © 2002 by
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FIGURE 1.9 Subthreshold leakage cur
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FIGURE 1.13 Epitaxial channel [9].
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gate length reduction was accelerat
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of the prediction. Until only sever
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FIGURE 1.22 Clarke number of elemen
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1.5 Source and Drain Figure 1.25 sh
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FIGURE 1.27 Retrograde profile. FIG
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TABLE 1.6 Trend of Interconnect by
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TABLE 1.9a Trend of DRAM Cell: Stac
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FIGURE 1.36 Trend of gate length. F
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References 1. D. Kahng and M. M. At
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40. B. H. Lee, R. Choi, L. Kang, S.
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outputs of the gate regardless of t
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FIGURE 2.4 circuit. This is the bas
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FIGURE 2.8 Two different realizatio
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FIGURE 2.12 Multifunction circuitry
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Dynamic Logic Circuits The basic id
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transistors in the pull-down networ
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In Fig. 2.21(d), the cross-coupled
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FIGURE 2.23 Different configuration
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In some literature, the authors lik
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Concluding Remarks The feature size
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FIGURE 2.30 Other pass-transistor c
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FIGURE 2.34 Dual-rail, pass-transis
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Shannon expansion, as shown below,
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FIGURE 2.41 Logic circuit for Out =
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FIGURE 2.45 Example decomposed BDD.
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FIGURE 2.50 Diffusion-area sharing
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FIGURE 2.54 Relationship between co
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29. Shiple, T. R., Hojati, R., Sang
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FIGURE 2.58 DTMOS devices: (a) stan
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the design into a BDD representatio
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FIGURE 2.63 Circuit diagram of 2-in
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FIGURE 2.67 Synthesis of 2-input AN
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pass-transistor logic, constrained
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16. Bryant, R., Graph-based algorit
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As shown in Fig. 2.79, the MOSFET d
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n + SiO 2 FIGURE 2.80 No reverse bo
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structures are a powerful solution
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SiO 2 Epitaxial Si Double Layered P
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PD-SOI Application to High-Performa
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LO FIGURE 2.91 History effects. sta
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weight, lower cost, a wireless inte
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TABLE 2.7 Performance of sub-1 V MT
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X X FIGURE 2.99 1 V A/D converter u
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When the communication range is 10
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13. Nakashima, S., et al., Thicknes
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FIGURE 3.1 Conventional ECL circuit
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FIGURE 3.4 FIGURE 3.5 IPULL-DOWN, f
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FIGURE 3.7 V REG voltage regulator
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FIGURE 3.10 Layout of inverter gate
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FIGURE 3.14 Power consumption versu
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I/O Pads, is 60 mW for the multiple
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FIGURE 3.21 Maximum data rate vs. V
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John C. McCallum National Universit
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enchmark took between 15.7 and 5115
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The improvements in line widths, ch
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performance. Extensive lists of SPE
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TABLE 4.6 Functions of Memory and S
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Memory Price ($/MB) FIGURE 4.3 Cost
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TABLE 4.8 Disk Drive Characteristic
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4.6 Summary The performance of comp
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53. Curnow, H. J., and Wichmann, B.
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Computer Systems and Architecture
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advances that have been made in dev
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Server Types Servers are optimized
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Total Cost of Ownership Another con
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edundant memory-bit steering, and s
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majority of the users. Hardware opt
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processor implementations. In later
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FIGURE 5.7 an operand. For larger c
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Example 2 This example contrasts th
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Unlike the Defoe, the IA-64 archite
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This 3-phase approach fails to expl
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6. Scott Rixner, William J. Dally,
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Shared-memory vector architectures
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The vector ISA usually fixes the ma
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FIGURE 5.12 A vector unit construct
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use of loops optimized for certain
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9. Espasa, R., Advanced Vector Arch
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thread management (including run-ti
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In the message passing model, inter
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multithreaded hardware, possibly by
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synchronization) and usually contai
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a common register space, it is impo
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FIGURE 5.16 When a load request is
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list a few helpful references to wh
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38. S. Wallace, B. Calder, and D. T
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Of course, SIMD machines have limit
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computation, it will decrease execu
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FIGURE 5.19 An 8 × 8 baseline netw
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Since then, we have seen constant e
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Stack: Data: Text: Virtual Space FI
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FIGURE 5.25 Shared memory. Shared m
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0 2 GB Text Init. Data Bss Heap . .
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In general, if the necessary transl
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Mark Smotherman Clemson University
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Studies of Instruction-Level Parall
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Modern Designs Most high-performanc
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The principle of register renaming
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FIGURE 6.2 issued into the RS, (ii)
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Issue Dispatch FIGURE 6.4 The proce
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FIGURE 6.6 Scope of register renami
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FIGURE 6.9 State transition diagram
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Thus, the maximal number of instruc
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In addition, if rename buffers are
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it, whose role will be explained su
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As Fig. 6.13 shows, the latest proc
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for recovery. Both processors incor
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FIGURE C. The principle of direct i
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13. White, S. and Reysa, J., PowerP
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FIGURE 6.14 A branch flowing throug
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is that mispredictions limit the pr
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fetch engine to identify which inst
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FIGURE 6.17 A schematic for a bimod
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FIGURE 6.20 A schematic for a GAg g
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FIGURE 6.22 A schematic for a hybri
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time this branch is seen, those bit
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FIGURE 6.23 Branch prediction accur
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11. Price, C., MIPS IV Instruction
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transporting digital bits, whereas
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FIGURE 6.25 The system architecture
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Finally, because the main task of n
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Pradip Bose IBM T. J. Watson Resear
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frequency © 2002 by CRC Press LLC
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The “mips” metric for performan
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Hence, in this paper, we do not dwe
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FIGURE 7.4 Parallel SIMD architectu
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dynamic prediction of such idle mod
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FIGURE 7.7 High-level block-diagram
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(measured as a performance over pow
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Steady-state BIPS FIGURE 7.9 Perfor
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8. Larson, A. G., “Cost-effective
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Jozo J. Dujmović San Francisco Sta
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x FIGURE 8.1 Movement of the disk I
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The critical distance x ∗ is Ther
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Hence, the average seek time for th
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FIGURE 8.4 Four-parameter exponenti
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Access Time [ms] 2 0 0 FIGURE 8.6 M
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TABLE 8.1 Classification of Eight B
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The traditional load independent me
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Response Time [seconds] 290 270 250
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FIGURE 8.14 Prediction errors e(p)
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8.2 Performance Evaluation: Techniq
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is generally the most important mea
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tool to profile programs on the Alp
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driven simulation has two major pro
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A variety of profiling tools exist
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SPLASH, the SPLASH suite was create
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different types and complexity eith
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Table 8.8 provides sources for the
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37. MediaBench benchmarks, http://w
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(a) Instruction Cache (b) Trace Cac
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PE 0 Local Register File local bypa
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The large trace processor instructi
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11. S. Melvin, M. Shebanow, and Y.
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complement numbers. Sign magnitude
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where ak, bk, and ck are the inputs
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k + 1, etc. Extending to a third st
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a 12:15 b 12:15 4-Bit RCA s 12:15 F
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FIGURE 9.8 Two’s complement subtr
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FIGURE 9.10 Unsigned 6 by 6 array m
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Digit Recurrent Division The most c
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FIGURE 9.14 Nonrestoring division.
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The Newton-Raphson division algorit
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FIGURE 9.18 Floating-point addition
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9.2 Fast Adders and Multipliers Gen
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FIGURE 9.20 Half-adder circuit. is
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gi pi FIGURE 9.22(b) Carry skip cir
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Assuming that a single level of the
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Array-Type Multiplier The simplest
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p1i,j p2i,j p3i,j p4i,j FIGURE 9.27
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The partial product PP j is to be c
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The sum SGN of the whole extended b
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FIGURE 9.31 54 × 54-bit parallel m
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6. Svensson, C. and Tjarnstrom, R.,
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Design Techniques III 10 Timing and
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FIGURE 10.1 Typical chip interface.
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Loop Components PLLs and DLLs share
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delay is some fraction of the input
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esults from the voltage across the
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© 2002 by CRC Press LLC TABLE 10.2
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db(H( ω)) FIGURE 10.6 PLL closed-l
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ω )/G O) db(T(ω ph(T( )/π) FIGUR
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Phase Margin (deg) FIGURE 10.10 PLL
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FIGURE 10.11 Measured PLL jitter hi
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FIGURE 10.13 DLL output jitter sens
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FIGURE 10.18 PLL output jitter sens
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Active supply filters employ amplif
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FIGURE 10.19 Single-ended delay ele
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Frequency (GHz) FIGURE 10.23 Freque
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FIGURE 10.25 Push-pull charge pump.
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Circuit Summary In general, all DLL
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5. T. Lee, et al., “A 2.5V CMOS D
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introduced in [3], is used to repre
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FIGURE 10.31 Setup and hold time ti
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FIGURE 10.34 Max-timing diagrams fo
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FIGURE 10.37 Time borrowing for sin
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FIGURE 10.39 Max-timing for single-
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Min-Timing In contrast to max-timin
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FIGURE 10.46 Min-timing diagrams fo
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FIGURE 10.49 Edge-triggered, flip-f
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FIGURE 10.51 FIGURE 10.52 Max-timin
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FIGURE 10.53 Transparent-high latch
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FIGURE 10.57 Complementary TSPC tra
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FIGURE 10.61 A positive, edge-trigg
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FIGURE 10.66 Pulsed latches. FIGURE
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assigned, based on the subcircuit t
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FIGURE 10.71 Scan chain for dual-ph
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and SEB, which are complementary, c
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when used as a flip-flop, the NAND3
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FIGURE 10.75 Integrated memory for
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Memory Cell Bit# Bit FIGURE 10.78 A
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FIGURE 10.80 Modeling process varia
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FIGURE 10.83 A column circuit. FIGU
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advantage of this circuit, compared
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K. Wayne Current University of Cali
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11.2 Nonvolatile Multiple-Valued Me
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Multiple-Valued EEPROM and Flash Me
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direct properly scaled and logicall
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Current comparators are a critical
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FIGURE 11.4 Current-mode CMOS quate
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FIGURE 11.6 Current-mode CMOS quate
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observed with these circuits are ab
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FIGURE 11.11 Current-mode CMOS quat
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FIGURE 11.12 Current-mode CMOS latc
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FIGURE 11.14 Current-mode CMOS anal
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esults confirm the DC transfer func
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19. T. T. Dao, “Threshold I2L and
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FIGURE 12.1 Device technologies use
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selected depending on the number of
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Architecture of Newer Generation FP
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FIGURE 12.6 An example of a simple
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tools, the + 1 operation is a speci
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download the programming data to th
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FIGURE 13.1 High-performance microp
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FIGURE 13.4 TABLE 13.1 combinationa
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accurate wire modelling while limit
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FIGURE 13.6 Dual-rail, multiple-out
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FIGURE 13.10 Effect of output inver
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FIGURE 13.11 Unfooted dynamic 4:1 m
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(4) the limit of designers to manag
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© 2002 by CRC Press LLC IV Design
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FIGURE 14.1 FIGURE 14.2 newer semic
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The cost impact of power consumptio
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In any case, the move toward “Gre
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This static current is obviously un
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14.2 Power Estimation As we saw in
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lock as a function of various param
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FIGURE 14.8 Sleep transistors to co
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FIGURE 14.12 Data enabling. In addi
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Power Reduction through CAD Tools P
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AMPS AMPS is a circuit power optimi
Page 534 and 535: Masayuki Miyazaki Hitachi, Ltd. 15.
Page 536 and 537: 15.3 Supply Voltage Management Supp
Page 538 and 539: FIGURE 15.4 MT-CMOS balloon circuit
Page 540 and 541: FIGURE 15.9 EVT-CMOS circuit design
Page 542 and 543: FIGURE 15.12 VT-CMOS block diagram
Page 544 and 545: FIGURE 15.15 SA-V t CMOS scheme wit
Page 546 and 547: FIGURE 15.17 Floating-point datapat
Page 548 and 549: Vivek De Intel Corporation Ali Kesh
Page 550 and 551: FIGURE 16.3 n-channel ID vs. VG sho
Page 552 and 553: Gate-Induced Drain Leakage (I 4) GI
Page 554 and 555: FIGURE 16.7 Two-nMOS stack in a two
Page 556 and 557: FIGURE 16.11 Four-input NAND NMOS s
Page 558 and 559: FIGURE 16.12 Distribution of standb
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Page 564 and 565: Thomas D. Burd University of Califo
Page 566 and 567: the parameter to be maximized since
Page 568 and 569: 17.3 Dynamically Varying Voltage If
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Page 572 and 573: FIGURE 17.7 DVS improvement for UI
Page 574 and 575: FIGURE 17.10 Measured throughput vs
Page 576 and 577: FIGURE 17.12 Sources of noise margi
Page 578 and 579: FIGURE 17.15 Ring oscillator adapti
Page 580 and 581: FIGURE 17.17 Sense-amp delay variat
Page 582 and 583: Christian Piguet CSEM: Centre Suiss
Page 586 and 587: TABLE 18.2 Looped 8-bit Multiply Pr
Page 588 and 589: FIGURE 18.4 new architecture paradi
Page 590 and 591: FIGURE 18.6 FIGURE 18.7 the second
Page 592 and 593: FIGURE 18.9 FIGURE 18.10 With latch
Page 594 and 595: 18.6 Low-Power Memories As memories
Page 596 and 597: connected to the main bitline (only
Page 598 and 599: is today only about a factor of 2 d
Page 600 and 601: Katsunori Seno SONY Corporation 19.
Page 602 and 603: FIGURE 19.2 FIGURE 19.3 This is a c
Page 604 and 605: FIGURE 19.6 FIGURE 19.7 FPGA sacrif
Page 606 and 607: FIGURE 19.9 RAWn precharge FIGURE 1
Page 608 and 609: a fixed given standard. References
Page 610 and 611: Hendrawan Soeleman Purdue Universit
Page 612 and 613: for a short period of time when bot
Page 614 and 615: Total Average Power Putting togethe
Page 616 and 617: Signal Probability Calculation In c
Page 618 and 619: Example Given y = x 1 + x 2. Find P
Page 620 and 621: A B F FIGURE 20.7 Unfactorized and
Page 622 and 623: etween successive transitions is a
Page 624 and 625: FIGURE 20.9 A logic gate and its co
Page 626 and 627: Results Using Probabilistic Techniq
Page 628 and 629: FIGURE 20.12 Probabilistic and stat
Page 630 and 631: 14. VLSI Microprocessors: A Guide t
Page 632 and 633: 0 V to a voltage V in time T throug
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a small fraction of circuit nodes t
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FIGURE 21.6 (a) E-R latch, (b) timi
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FIGURE 21.8 Potential E-R latch for
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The only difference between the two
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FIGURE 21.14 (a) Clock-powered stat
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FIGURE 21.17 The three drivers used
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FIGURE 21.20 Energy-delay product (
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FIGURE 21.22 AC-1 clock-driver sche
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clock-powered nodes accounted for 8
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Two generations of clock-powered mi
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29. Athas, W. C., Tzartzanis, N., M
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Wayne Wolf Princeton University 22.
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so a CPU could be built in reconfig
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optimized processes. Although embed
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FIGURE 22.4 they are most useful wh
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• How should processes be allocat
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25 memory system activity. If the c
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Jonathan W. Valvano University of T
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FIGURE 23.2 6808, I/O ports A and B
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personnel so that they are proficie
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BDM can provide the ability to obse
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minor modifications to the finite s
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Many components are included in a d
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will saturate resulting in a bang-b
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Two approaches are used to synchron
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Fred J. Taylor University of Florid
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The output of a linear system havin
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FIGURE 24.2 Effects of windowing an
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frequency range ±f Nyquist = ±f s
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performance, complexity, and precis
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overflows of intermediate sums. Tha
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24.7 Applications “DSP” has bec
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DSP (Digital Signal Processor) or D
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PC as a Terminal (Modem) The PC is
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characteristics: • Fixed pictures
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HDTV (and Digital Television) If th
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Modem Banks This is the first of th
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25.7 Automotive, Industrial Althoug
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36. MITEL Semiconductor: www.semico
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26.2 Digital Filters The theory of
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|H | 1 FIGURE 26.1 Frequency select
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TABLE 26.1 Filter Design Comparison
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frequency response involves some al
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Impulse Response 0.2 0.15 0.1 0.05
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This constrained magnitude problem
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FIGURE 26.8 Block diagram of the ge
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11. Ikehara, M., Tanaka, H., and Ku
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Adam Dabrowski Poznan University To
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−12 2 The reference in this case
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FIGURE 27.1 Two-band filter bank: (
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FIGURE 27.5 Critical bandwidth and
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FIGURE 27.7 Threshold of audibility
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FIGURE 27.10 Critical band index in
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FIGURE 27.13 Simplified model of th
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All described masking effects are e
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where From Eqs. (27.32) and (27.33)
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eal-time. Although floating-point p
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FIGURE 27.19 Overlapped, power comp
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FIGURE 27.21 Symmetrical FIR filter
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In the MPEG-1 encoder an efficient
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These first two approaches can be m
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FIGURE 27.27 ADPCM: (a) encoder, (b
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FIGURE 27.30 General scheme of the
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A new standard MPEG-7, named the mu
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FIGURE 27.32 AC-3 encoder. FIGURE 2
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29. Marven, C. and Ewers, G., A sim
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FIGURE 28.1 FIGURE 28.2 of the huma
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FIGURE 28.5 image of reasonable qua
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Consider the case of a simple 2-D
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FIGURE 28.8 A sampled spatiotempora
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oth high spatial frequency componen
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If it were separable (that is, H(ξ
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The first hypothesis (the less plau
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FIGURE 28.17 The real (top) and ima
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FIGURE 28.18 The resolution of a ti
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FIGURE 28.20 Motion estimation by b
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where the superscripts n and n + 1
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must be found via a finite set of o
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The methods in this subsection are
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FIGURE 28.28 The split phase. Using
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35. Y.-T. Wu, T. Kanade, J. Cohn, a
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29.2 Power Dissipation in Digital C
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additional power benefits. Efficien
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Power savings are higher than simpl
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A priori knowledge of data stream d
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FIGURE 29.7 DCT Chip [my DCT] avera
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19. S. Uramoto et al. A 100 MHz 2-D
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Anna Hać University of Hawaii 30.1
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Using TCP/IP also makes the network
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this is for one mobile host which i
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TDMA Time-division multiple access
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path delay. The two measures of the
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are under the control of the system
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the bandwidth reserved in the targe
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Chik-Kong Ken Yang University of Ca
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FIGURE 31.3 attenuation (dB) -3.0 -
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FIGURE 31.5 to handle large voltage
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p_o V bias FIGURE 31.8 High-impedan
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out[n] a0 FIGURE 31.11 Transmitter
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FIGURE 31.15 Receiver design using
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digitally by first feeding the inpu
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FIGURE 31.19 90 o locking using XOR
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Power of these links is becoming an
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46. Takahashi, T. et al., “A CMOS
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Many computer programs exhibit some
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32.3 Related Memory Models, Hierarc
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32.6 External Sorting and Related P
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uns, each striped across the disks.
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Matrix transposition is the special
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of satellite images is over one ter
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TABLE 32.3 Best Known I/O Bounds fo
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e accessed directly in a single I/O
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implementations of priority queues
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By the reduction in [52], a data st
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set of experiments on various text
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3. A. Acharya, M. Uysal, and J. Sal
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44. J. L. Bentley and J. B. Saxe. D
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85. P. Ferragina and F. Luccio. Dyn
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128. V. Kumar and E. Schwabe. Impro
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173. H. Samet. The Design and Analy
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Peter J. Varman Rice University 33.
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need for fast transfers, up to 1 Gb
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In contrast to prefetching that mas
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The ERF algorithm was analyzed in [
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increment lowestPriorityOnDisk(disk
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External or out-of-core algorithms
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33. M. Kallahalla and P. J. Varman.
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advanced, reaching the point where
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FIGURE 34.3 FIGURE 34.4 defines the
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FIGURE 34.5 Trellis representation
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FIGURE 34.7 Data and servo sectors.
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References 1. S. H. Charrap, P. L.
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High-frequency noise is then remove
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The various components of (34.3) ar
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sequences are more complex, and occ
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ange of 10 −12 -10 −15 . Anothe
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strategies are reviewed, which have
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FIGURE 34.13 Magnitude response for
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taps as an approximation of the Typ
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FIGURE 34.18 CTF BER performance de
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TABLE 34.1 Examples of Equalizers I
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(i) Symbol rate VCO based timing re
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Symbol Rate Timing Recovery Schemes
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where B = B 1 + B 2 + 1 is the size
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in � out � d(k) FIGURE 34.26 Ti
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�(k) z -L FIGURE 34.27 Linearized
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10 −4 and 10 −2 . The steady-st
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16. J. Sonntag, et al., “A high s
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y a special sequence known as the a
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FIGURE 34.36 An example of two Gray
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track n track n +1 FIGURE 34.38 The
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FIGURE 34.40 The phase format. Posi
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increase linear density while mitig
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FIGURE 34.43 Two equivalent constra
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FIGURE 34.44 Possible pairs of sequ
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Distance δ min,C can be bounded as
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FIGURE 34.45 Standard concatenation
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30. E. Soljanin, “On-track and of
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The next block is PRE. What is PR?
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In the above example, we see that s
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FIGURE 34.52 Feedback detector. Cat
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FIGURE 34.54 Decision feedback equa
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esponse (this is also valid for dif
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its use, while the computational, o
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FIGURE 34.58 Viterbi algorithm dete
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Noise-Predictive Maximum Likelihood
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The error event likelihoods are cal
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Metric-First Algorithms Metric-firs
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termination at the same time. Howev
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13. J. Hagenauer, “Applications o
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Given a code C of length n and dime
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Notice that, although a code may ha
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Not many perfect codes exist. In th
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Theorem 1 (Shannon) For any � > 0
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If we write the codewords as polyno
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Let © 2002 by CRC Press LLC 1 1 K
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which, in polynomial form, is Let E
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m Σl=0 because a l = (a m+1 − 1)
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Evaluating the syndromes, we obtain
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FIGURE 34.63 Interleaving m times o
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Operating System © 2002 by CRC Pre
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systems, the most notable example b
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35.3 Components of Distributed Oper
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Message-passing IPC shares many cha
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process at any arbitrary stage in i
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Few attempts were made in the past
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alternate years with SOSP), and the
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© 2002 by CRC Press LLC 42 Mobile
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FIGURE 36.1 were introduced; howeve
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FPGAs by providing on-chip memory f
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FIGURE 36.3 There is a considerable
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FIGURE 36.4 The general form of the
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FIGURE 36.6 If a VPB can cover all
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John Morris University of Western A
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FIGURE 37.1 Simplified block diagra
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inverters, and the programmable mul
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Programmable Active Memories (PAM)
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measured in megabits, not megabytes
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from modern FPGAs, e.g., Altera’s
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Regularity A processing pipeline wi
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Other Languages Other routes from h
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29. Bergmann, N.W., and Dawood, A.,
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FIGURE 37.8 Basic architectures for
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Selected Applications Several class
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Development Systems Developing appl
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implementation. Reconfigurable or r
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The designer starts the generation
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lock but allows multiple instructio
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data-types that are mapped to TIE r
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Conclusions Configurable and extens
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FIGURE 38.1 Average vehicle speed.
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AHS means advanced cruise-assist hi
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TABLE 38.3 navigation systems VICS
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FIGURE 38.9 FIGURE 38.10 a map data
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FIGURE 38.13 The four basic functio
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Support of Safe Driving System The
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System evaluation, the fourth issue
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FIGURE 38.18 Summarizing the three
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uilder tools serving to build MMI o
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FIGURE 38.23 FIGURE 38.24 automaker
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FIGURE 38.26 FIGURE 38.27 The first
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FIGURE 38.30 FIGURE 38.31 a kind of
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To Probe Further In this field, the
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FIGURE 39.1 of more versatile media
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1 • 3DNow! 1 [11,12] from AMD,
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FIGURE 39.6 In the packed add instr
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If saturation arithmetic is used in
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TABLE 39.1 Examples of Operations T
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FIGURE 39.10 PAVG R c, R a, R b: Pa
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FIGURE 39.13 Packed compare instruc
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FIGURE 39.17 Packed multiply high i
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FIGURE 39.20 Packed multiply left i
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FIGURE 39.23 In the packed multiply
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TABLE 39.4 Packed Integer Multiplic
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Subword Permutation Instructions In
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is n log 2(n). Table 39.6 shows how
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FIGURE 39.33 Mix left instruction.
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TABLE 39.7 Subword Permutation Inst
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TABLE 39.9 IA-64 uses FPMA and FPMS
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The two-bit result field is written
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source register. These three FP mix
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13. Motorola, “AltiVec technology
Page 1118 and 1119:
FIGURE 39.48 ManArray 1 × 2 core e
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FIGURE 39.50 Hypercube interconnect
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FIGURE 39.53 Host DSP software laye
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Benchmark Data Type Performance 256
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FIGURE 39.56 Simplified schematic o
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Gaming applications often require a
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system, and the application program
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FIGURE 39.60 FIGURE 39.61 FIGURE 39
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FIGURE 39.64 shifting place limits
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FIGURE 39.66 pitch Address Looping
Page 1138 and 1139:
FIGURE 39.69 gain of the filter. It
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as a core to integrate onto the sam
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7. Rossum, D., Constraint based aud
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FIGURE 39.74 Procedure for simulate
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The fitness value of an individual
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FIGURE 39.77 The tabu list can be v
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Intermediate-term memory component
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FIGURE 39.81 Selection. FIGURE 39.8
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Work on parallelization of the tabu
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Acknowledgment The authors acknowle
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47. L. K. Grover. A new Simulated A
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93. E. M. Rudnick, J. H. Patel, G.
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138. Youn-Long Lin, Yu-Chin Hsu, an
Page 1164 and 1165:
This architecture allowed for large
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FIGURE 40.3 40.3 Application Server
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FIGURE 40.5 applications. CORBA cur
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FIGURE 40.8 The application server
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FIGURE 40.10 The proposed architect
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cost at the front end. The ideal ap
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FIGURE 40.12 Client-server and netw
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Yoshiaki Hagiwara Sony Corporation
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FIGURE 41.2 This corresponds to the
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FIGURE 41.5 Buried channel CCD stru
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FIGURE 41.8 Applications of CCD and
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sensor (1100 K pixel) Microphone ×
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�� FIGURE 41.14 Form com
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FIGURE 41.16 Stack technology. Link
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1st EmDRAM Product FIGURE 41.19 Emb
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FIGURE 41.23 Em-DRAM process techno
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John F. Alexander University of Nor
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Several reasons exist for mentionin
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sort of local area network. Support
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Technological hurdles must be overc
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FIGURE 42.1 Block diagram of (a) ge
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FIGURE 42.3 Alternative FIR filter
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FIGURE 42.5 Polyphase filter struct
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3. E. Dahlman, Bjorn Gudmundson, M.
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TABLE 42.1 Categorizing Reusable Co
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FIGURE 42.11 Internet growth. FIGUR
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FIGURE 42.13 Software for VoIP SoC.
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FIGURE 42.17 Bandwidth trends. FIGU
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The interconnections between the va
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FIGURE 42.21 A typical communicatio
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carry information over longer dista
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however, it is not uncommon that so
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node, to which the user is connecte
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its information. Intuitively, this
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This issue is referred to as latenc
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Evolution of Standard Image/Video C
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FIGURE 42.26 Sequence of zigzag-cod
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FIGURE 42.29 150th Frame of origina
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FIGURE 42.31 Data partitioning for
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for transmitting a predictively cod
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42.6 Pen-Based User Interfaces—An
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FIGURE 42.35 The handwriting recogn
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• No toggling between edit/contro
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FIGURE 42.39 Boxplots of time to en
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0 … 9 ( ) -
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is using the SMIL generic media ref
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FIGURE 42.47 Example of pen-and-pap
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slots specifying pieces of informat
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most stringent demands for low-powe
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FIGURE 42.51 MIPS requirement of se
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FIGURE 42.54 von Neumann architectu
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FIGURE 42.57 Dual Mac architecture
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FIGURE 42.59 Two data path variatio
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FIGURE 42.60 Basic pipeline archite
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References 1. Bahl L., Cocke J., Je
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Random Oracle Model One direction o
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at the end of its usefulness. A new
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function and verification function
Page 1280 and 1281:
underlies the Diffie-Hellman key ag
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31. Dolev, D., Dwork, C., and Naor,
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R. Chandramouli Synopsys Inc. 44.1
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many deficiencies in the design may
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impact the performance and test ove
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FIGURE 44.4 FIGURE 44.5 It becomes
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SoC methodologies require synchroni
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This method, however, lacks the app
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FIGURE 45.2 Input formats of MILEF
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FIGURE 45.3 FIGURE 45.4 Robustness
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FIGURE 45.5 In Fig. 45.5 a simple e
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difficult to identify for overcurre
Page 1304 and 1305:
General Approach in Comparison with
Page 1306 and 1307:
FIGURE 45.10 phase—the propagatio
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shorter test sequence could possibl
Page 1310 and 1311:
Looking at results of Table 45.6, i
Page 1312 and 1313:
45.4 Summary Automatic test pattern
Page 1314 and 1315:
41. F. Brglez, H. Fujiwara: A neutr
Page 1316 and 1317:
FIGURE 46.1 Rule of ten in testing
Page 1318 and 1319:
FIGURE 46.5 FIGURE 46.6 of the DUT.
Page 1320 and 1321:
FIGURE 46.7 generate tests for ever
Page 1322 and 1323:
FIGURE 46.9 FIGURE 46.10 behavioral
Page 1324 and 1325:
Z. Stamenković University of N. St
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FIGURE 47.2 Murphy’s Model The mo
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where k is the total number of crit
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FIGURE 47.5 Definition of IC critic
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distribution [34,35]: © 2002 by CR
Page 1334 and 1335:
and, in the case of w = X 2 − X 1
Page 1336 and 1337:
Algorithm • Input: a singly linke
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TRACIF takes a CIF file as input an
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TABLE 47.2 Critical Area Extraction
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Also, the critical areas for lithog
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(enhancement of the process cleanli
Page 1346 and 1347:
28. Corsi, F. and Martino, S., Defe
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U. Glaeser

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