U. Glaeser

for a short period of time when both PMOS and NMOS transistors are conducting simultaneously when
the logic gates are switching.
Depending on the design requirements, there are different power dissipation factors that need to be
considered. For example, the peak power is an important factor to consider while designing the size of the
power supply line, whereas the average power is related to cooling or battery energy consumption requirements.
We focus on the average power consumption in this chapter. The peak power and average power
are defined in the following equations:
© 2002 by CRC Press LLC
Ppeak
= Ipeak
· Vsupply
Static Power Component
and
Paverage
=
In CMOS circuit, no conducting path between the power supply rails exists when the inputs are in an
equilibrium state. This is due to the complimentary feature of this technology: if the NMOS transistors
in the pull-down network (PDN) are conducting, then the corresponding PMOS transistors in the pullup
network (PUN) will be nonconducting, and vice-versa; however, there is a small static power consumption
due to the leakage current drawn continuously from the power supply. Hence, the static power
consumption is the product of the leakage current and the supply voltage ( Pstatic
= Ileakage
· Vsupply),
and
thus depends on the device process technology.
The leakage current is mainly due to the reverse-biased parasitic diodes that originate from the sourcedrain
diffusions, the well diffusion, and the transistor substrate,
and the subthreshold current of the
transistors. Subthreshold current is the current which flows between the drain and source terminals of
the transistors when the gate voltage is smaller than the threshold voltage ( Vgs
< Vth).
For today and
future technologies, the subthreshold current is expected to be the dominant component of leakage
current. Accurate estimation of leakage current has been considered in [13].
Static power component is usually a minor contributor to the overall power consumption. Nevertheless,
due to the fact that static power consumption is always present even when the circuit is idle, the
minimization of the static power consumption is worth considered by completely turning off certain
sections of a system that are inactive.
Dynamic Power Component
Dynamic power consumption occurs only when the logic gate is switching. The two factors that make
up the dynamic power consumption are the charging and discharging of the output load capacitances
and the switching transient current. During the low-to-high transition at the output node of a logic gate,
the load capacitance at the output node will be charged through the PMOS transistors in PUN of the
circuit. Its voltage will rise from GND to
V
supply
1 T
-- ( Isupply() t ⋅ Vsupply) dt
T ∫
. An amount of energy, Cload ⋅ Vsupply, is drawn from the
power supply. Half of this energy will then be stored in the output capacitor, while the other half is
dissipated in the PMOS devices. During the high-to-low transition, the stored charge is removed from
the capacitor, and the energy is dissipated in the NMOS devices in the PDN of the circuit. Figure 20.2
illustrates the charging and the discharging paths for the load capacitor. The load capacitance at the
output node is mainly due to the gate capacitances of the circuits that are being driven by the output
node (i.e., the number of fanouts of the output node), the wiring capacitances, and the diffusion
capacitances of the driving circuit.
Each switching cycle, which consists of charging and discharging paths, dissipates an amount of energy
2
equals to Cload ⋅ Vsupply. Therefore, to calculate the power consumption, we need to know how often the
gate switches. If the number of switching in a time interval t(
t → ∞)
is B,
then the average dynamic
power consumption is given by
P dynamic
1
2
-- Cload Vsupply B
2
1 1
2
= ⋅ ⋅ ⋅ ⋅ -- =
-- ⋅ Cload ⋅ Vsupply ⋅ A
t 2
0
2