U. Glaeser

FIGURE 44.1 Core access through wrapper isolation.
44.2 Current Test Practices
Current test practices consist primarily of ATE-based external test approaches. They range from manual
test development to scan-based test. Most of the manual test development efforts depend on fault simulation
to estimate the test coverage. Scan-based designs are becoming very common, although their capacity
and capability to perform at-speed test are being increasingly affected by physical limitations.
Scan-Based Test
Over the past decade, there has been an increased use of the scan DFT methodology across a wide variety of
designs. One of the key motivations for the use of scan is the resulting ability to automatically generate test
patterns that verify the gate or transistor level structures of the scan-based design. Because test generation is
computationally complex for sequential designs, most designs can be reconfigured in test mode as combinational
logic with inputs and outputs from and to scannable memory elements (flip-flops) and primary I/O.
Different types of scan design approaches include mux-D, clock scan, LSSD, and random access scan [1].
The differences are with respect to the design of the scannable memory elements and their clocking
mechanisms.
Two major classes of scan design are full scan and partial scan. In the case of full scan, all of the
memory elements are made to be scannable, while in the case of partial scan, only a fraction of the
memory elements, based on certain overhead (performance and area) constraints, are mapped into scan
elements. Because of its iterative nature, the partial scan technique has an adverse impact on the design
cycle. Although full scan design has found wider acceptance and usage, partial scan is seen only in designs
that have very stringent timing and die size requirements. A major drawback with scan is the inability
to verify device performance at-speed. In general, most of the logic related to scan functionality is designed
for lower speed.
Back-End Scan Insertion
Traditional scan implementation depended on the “over-the-wall” approach, where designers complete
the synthesis and hand off the gate netlist to the test engineer for test insertion and automatic test pattern
generation (ATPG). Some electronic design automation (EDA) tools today help design and test engineers
speed the testability process by automatically adding test structures at the gate level. Although this
technique is easier than manual insertion, it still takes place after the design has been simulated and
synthesized to strict timing requirements. After the completed design is handed over for test insertion,
© 2002 by CRC Press LLC
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