U. Glaeser

(enhancement of the process cleanliness, etc.) resulted in the final wafer yield increase of over 10%. Such
a yield improvement could not be achieved by any investment in any other critical process step.
The usual approach to the IC production control is based on the defect or fault density measurements,
and does not take into account the dependence on the complexity of a given IC type. Therefore, the lot
of wafers may be stopped regardless of the IC type. Namely, a given defect density level can enable a
decent yield (and price) of simpler IC chips, but it may not be sufficient to achieve the desired yield and
price of more complex IC chips. The approach considered in this paper does not suffer of described
disadvantage. Moreover, it can be used to forecast and characterize yields of future products in order to
decide about investments that enable the desired final IC production yield.
In the considered example of production of IC Chip1, it is estimated that the mean and variance of
the wafer yield associated with p + -diffusion should be higher than 0.92 and lower than 3.5 × 10 −5 ,
respectively, in order to ensure the acceptable value of the final wafer yield. It can be seen from Fig. 47.14
that the currently established p + -diffusion process fulfills the imposed requirements; however, in the
case of production of IC Chip2, the same defect density associated with the p + -diffusion process has
resulted in the mean of the wafer yield 0.792 and its variance 2.23 × 10 −4 , both of them being out of
estimated limits presented in Fig. 47.14. Therefore, in order to achieve the competitive price with a
possible production of more complex IC Chip2, a further investment in p + -diffusion process should be
made.
47.5 Summary
Basic IC yield models (Murphy’s approach) and yield parameters (test structure yield, chip yield, and
wafer yield) are presented. Both defect density and defect size distributions are described. Using corresponding
in-line measurements of the test structure yields, the chip yield, associated with the ith critical
process step, is directly calculated; however, the chip yield is not sufficient for complete yield characterization,
and the wafer yield, defined as a ratio between the number of failure-free chips and the total
number of chips on a wafer, is predicted as well. We define the wafer yield as a distribution with two
statistical parameters: the mean and variance.
A local layout extraction approach for hierarchical extraction of the IC critical areas for point and
lithographic defects is described. The authors propose new expressions for definition of the circular parts
of critical areas for shorts and opens between IC patterns. Also, the Gamma distribution is proposed as
an approximation of the measured lithographic defect size distribution for estimating of the average
critical area. It is shown that the Gamma distribution provides good agreement with the measured data,
thus leading to a precise estimation of the critical area. Canonical coordinates (x 1, y 1) and (x 2, y 2) have
been defined for a geometrical representation of the equivalent critical areas for shortening two geometrical
objects and opening a geometrical object. Two kinds of data structures are used for the critical area
extraction. The first one is used for efficient object representation in the active list. A singly linked list
is chosen for the active list not only for its simplicity, but also for its speed and memory efficiency. The
second data structure is used for a list of coordinates of the critical areas. The extraction of critical areas
is carried out by an algorithm that solves this problem time proportional to n√n, on average, where n is
the total number of the analyzed geometrical objects (rectangles). This algorithm is a typical scan-line
algorithm with singly linked lists for storing and sorting the incoming objects. The performance of the
authors’ algorithm is illustrated on five layout examples by the analysis of CPU time consumed for
computing the critical areas applying a software tool system TRACIF/EXACCA/GRAPH.
The chip and wafer yields associated with each critical process step (i.e., each defect type) are determined
by making use of the above-described approach. The final wafer yield predictions are made as
well. An example of such a characterization of IC production process is described. It is shown that the
proposed approach can be used for modeling yield loss mechanisms and forecasting effects of investments
that are required in order to ensure a competitive yield of ICs. Our approach uses both wafer yield
parameters, the mean and variance, and enables sophisticated selection of IC types.
© 2002 by CRC Press LLC