U. Glaeser

FIGURE 42.15 Communications SoCs processing power and memory handwidth.
FIGURE 42.16 (a) Number of DSP processors per SoC. (b) Price per functional VoIP channel.
gates per chip will increase from one million in 1999 to 7 M in 2003. A major component in a communication
SoC is the embedded memory banks, which is also expected to increase from 1 to 16 Mbit. The
type of memory used will change from static RAMs (SRAM) to enhanced dynamic RAMs (EDRAM),
which are much more compact.
The processing power of these SoCs is also expected to increase as illustrated in Fig. 42.15. The
processing power is measured in million instructions per second (MIPs). It is predicted to grow from
100 to 1000 MIPs (dashed line) from 1999 to 2003. In same time period, the memory bandwidth (solid
line) will increase from 100 to 1000 Mbits. The growth of the number of DSP processors by SoC is shown
in Fig. 42.16(a). With all of this growth, it is interesting that the price of SoCs is estimated to decrease
according to the trend shown in Fig. 42.16(b).
Several predictions were given to the bandwidth of communication chips. Two of these predictions
are shown in Fig. 42.17. One assumes that the bandwidth will triple each year in the next 25 years as
illustrated by the solid line [George Dilder-Telecosm]. The other shows that the growth will be at the
rate of 8–16 times a year [SUN Microsystems]. In the 1990s, Bill Gates claimed that “we will have infinite
bandwidth in a decade of time [Gates 1994].”
System Latency
Latency is defined as the delay experienced a certain processing stage. The latency trends in Fig. 42.18
refer to the time taken to map the voice data into a packet to be transmitted. Three main types of latency
are usually identified:
© 2002 by CRC Press LLC