U. Glaeser

uffer can receive up to three results per cycle and can start retirement of up to three uops per cycle.
Retirement requires three cycles. Thus the overall pipeline has some 14 stages; but, because some of these
stages can overlap, the effect is a minimum latency of 12 cycles per instruction.
The Pentium 4 is a redesign of the core microarchitecture. The translation of IA-32 instructions into
uops is retained, but instead of repeatedly fetching, decoding, and translating recurring IA-32 instruction
sequences, the uops are stored in a trace cache for repeated access. The trace cache can hold up to 12 K
uops, and in a manner somewhat similar to the PowerPC 750 branch elimination logic, the trace cache
stores frequently-traversed sequences (i.e., “traces”) of uops with any predict-taken branches followed by
instructions from the predicted path. The trace cache can provide up to three uops per cycle, which are
then routed through reorder-buffer allocation logic, register-renaming logic, and then into uop queues for
scheduling. Up to six uops can be issued per cycle, and up to three uops can be retired per cycle. Part of
the aggressiveness of the design can be seen by the increase in the reorder buffer size from 40 entries in the
P6 core to 126 entries for the Pentium 4. The clock rate can also be aggressively increased on the Pentium 4,
since there are approximately double the number of pipeline stages in it as compared to the P6 core. By
cascading ALUs, two dependent addition or subtraction operations can be performed in each cycle.
References
1. Johnson, M., Superscalar Microprocessor Design, Prentice-Hall, Englewood Cliffs, NJ, 1991.
2. Tjaden, G., and Flynn, M., Detection of parallel execution of independent instructions, IEEE Trans.
Computers, C-19, 889, 1970.
3. Riseman, E., and Foster, C., The inhibition of potential parallelism by conditional jumps, IEEE Trans.
Computers, C-21, 1405, 1972.
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IEEE Trans. Computers, C-33, 968, 1984.
5. Hinton, G. et al., The microarchitecture of the Pentium 4 processor, Intel Technology Journal, available
on-line, 2001.
6. Schorr, H., Design principles for a high-performance system, in Proc. Symp. Computers and Automata,
New York, 1971, 165.
7. Agerwala, T., and Cocke, J., High performance reduced instruction set processors, Technical Report
RC12434, IBM Thomas Watson Research Center, 1987.
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9. Kennedy, A., et al., A G3 PowerPC superscalar low-power microprocessor, in Proc. COMPCON, San
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1
6.2 Register Renaming Techniques
Dezsö Sima
Introduction
Register renaming (or “renaming” for short) is a widely used technique in instruction level processors
(ILP) to remove false data dependencies between register operands of subsequent instructions in a straight
1–3
line code sequence. As false data dependencies we designate read-after-write (RAW) and write-afterwrite
(WAW) dependencies. If false data dependencies are removed, no related precedence requirements
constrain the execution sequence of the instructions involved. Thus, on an average, more instructions
are available for parallel execution per cycle, which increases processor performance.
1
Portions of this chapter reprinted with permission from Sima, D., The design space of register renaming techniques,
IEEE Micro, 20 Sept./Oct., 70, 2000. © 2000 IEEE
© 2002 by CRC Press LLC