U. Glaeser

FIGURE 31.16 Offset cancellation using digital controllable switchs (a) and using feedback control (b).
capacitors, C os. If data is encoded so that averaged dc is a constant (dc-balanced), a similar technique
finds the offset by averaging of the received data [22] instead of wasting a phase to short the inputs.
Noise
DAC
ctrl register
The main sources of noise for a receiver are mutual coupling between I/O signals and differences between
chip ground and board ground. Large image currents that flow through the supply pins to support the
output drivers cause significant voltage differences. 13 Some of the supply noise inevitably appears at the input
to the receiver. Signaling differentially and carefully routing the two signals together can effectively reduce
noise to the order of tens of millivolts. Supply noise couple capacitively as common-mode noise. Furthermore,
mutual coupling from other signals is at least partially compensated by coupling from its complement.
Single-ended signaling can achieve nearly the same performance if the return current supply connection
is brought on-chip, tightly coupled to the signal through a separate pin. The receiver’s reference can
be derived from the return connection, but this requires the same number of pins as differential signaling.
To save pins, most single-ended systems use the chip supplies (V dd and ground) to derive the reference.
Or, several receivers share a single return current connection. Unfortunately, since the reference signal
is shared, the capacitance between the supplies to the input pad and to the reference voltage differ. The
larger capacitance to the reference couples more high-frequency supply noise [26,42,46]. Single-ended
systems typically require larger input swings than differential systems for the same performance.
A band-limited receiving amplifier can filter some of the noise. One approach to control the bandwidth
is to bias the effective load transistors with a control signal that tracks the bit time. 14 To maintain constant
output swing, the bias current of the differential amplifier must also track. An ideal filter for square-wave
inputs averages the input signal over the bit time with an integrator 15 [43]. An integrating receiver replaces
the load elements with capacitors. The capacitors integrate the current that is switched by the input value.
At the end of the bit time, a comparator samples and compares the values on the capacitors before the
integrator is reset.
Receiver Equalization
With data rates above the bandwidth of the channel, an alternative to transmitter pre-emphasis is to build
the inverse channel filter at the receiver. Designers can increase the gain of the first amplifier at highfrequencies
to flatten the system response [45]. The required high-pass filter can also be implemented
13 On-chip bypass capacitance only reduces chip VDD to chip ground noise, and has no effect on the noise between
chip ground and board ground.
14
Similar to transmitter slew-rate control, one can leverage the fact that buffers in the clock generator have been
adjusted to have a bandwidth related to the bit rate [49].
15
Most signals are not perfect square waves. In addition to finite signal slew rate, bit boundaries contain timing
uncertainty. Integrating over a portion of the bit-time (“window”) can reduce noise.
© 2002 by CRC Press LLC
clk clk
Vo-
V i+
clk
clk
V o+
V i-
DAC
ctrl register
clk0 Vi Cos ref
clk1 clk1 _
Aos +
_
A o
(a) (b)
reset
d in0