U. Glaeser

FIGURE 12.7
until the next clock. In the second block of code in each model, a VHDL WITH SELECT concurrent
statement and a Verilog ALWAYS block assigns the output signal based on the current state (i.e., a Moore
state machine). This generates gates or combinational logic only with no flip-flops since there is no sensitivity
to the clock edge.
In the second example seen in Fig. 12.7, the hardware to be synthesized consists of a 16-bit registered
ALU. The ALU supports four operations, add, subtract, bitwise AND, and bitwise OR. The operation is
selected with the high two bits of ALU_control. After the ALU operation, an optional shift left operation
is performed. The shift operation is controlled by the low-bit of ALU_control. The output from the shift
operation is then loaded in a 16-bit register on the positive edge of the clock.
At the start of each of the VHDL and Verilog ALU models, the input and output signals are declared
specifying the number of bits in each signal. The top-level I/O signals would normally be assigned to
I/O pins on the FPGA. An internal signal, ALU_output, is declared and used for the output of the ALU.
Next, the CASE statements in both models synthesize a 4-to-1 multiplexer that selects one of the four
ALU functions. The + , −,
AND (&), and OR (|) operators in each model automatically synthesize a
16-bit adder/subtractor with fast carry logic, a bitwise AND, and a bitwise OR circuit. In most synthesis
© 2002 by CRC Press LLC
VHDL Model of ALU Verilog Model of ALU
entity ALU is
port(ALU_control : in std_logic_vector(2 downto 0);
Ainput, Binput: in std_logic_vector(15 downto 0);
Clock : in std_logic;
Shift_output: out std_logic_vector(15 downto 0));
end ALU;
architecture RTL of ALU is
signal ALU_output: std_logic_vector(15 downto 0);
begin
process (ALU_Control, Ainput, Binput)
begin
case ALU_Control(2 downto 1) is
when "00" => ALU_output ALU_output ALU_output ALU_output ALU_output