U. Glaeser

FIGURE 16.7 Two-nMOS stack in a two-input NAND
gate.
FIGURE 16.8 DC solution of two-nMOS stack.
Transistor Stack Effect
The “stack effect” refers to the leakage reduction effect in a transistor stack when more than one transistor
is turned off. The dynamics of the stack effect can be best understood by considering a two-input NAND
gate in Fig. 16.7. When both M1 and M2 are turned off, the voltage V m at the intermediate node is
positive due to the small drain current. Thus, the gate-to-source voltage of the upper transistor M1 is
negative, i.e., V gs1 < 0. The exponential characteristic of the subthreshold conductance on V gs greatly
reduces the leakage. In addition, the body effect of M1 due to V M > 0 further reduces the leakage current
as V t increases.
The internal node voltage V M is determined by the cross point of the drain currents in M1 and M2.
Since leakage current strongly depends on the temperature and the transistor threshold voltage, we
consider two cases: (1) high V t and room temperature at 30°C and (2) low V t and high temperature at
110°C. Figure 16.8 shows the DC solution of nMOS subthreshold current characteristics from SPICE
simulations. The leakage current of a single nMOS transistor at V g = 0 is determined by the drain current
of M1 at V M = 0. It is clear that the leakage current through a two-transistor stack is approximately an
order of magnitude smaller than the leakage of a single transistor. The voltage V M of the internal node
converges to ~100 mV, as shown in Fig. 16.8. The small V M (= drain-to-source voltage of M2) reduces
the DIBL, and hence increases V t of M2, which also contributes to the leakage reduction.
The subthreshold swing is proportional to kT . The slope decreases when the temperature T increases,
which moves the cross point (Fig. 16.8) upwards. Thus, the amount of reduction will be smaller at higher
temperature. The amount of reduction is also dependent on the threshold voltage V t, which is larger for
higher V t. For three- or four-transistor stacks, the leakage reduction is found to be 2–3 times larger in
both nMOS and pMOS. Results are summarized in Fig. 16.9. Note that reductions are obtained at the
room temperature, as we are only interested in standby mode.
The reduced standby stack leakage current is obtained under steady-state condition. After a logic gate
has a transition, the leakage current does not immediately converge to its steady-state value. Let us again
© 2002 by CRC Press LLC
Transistor Drain Current
1.E+03
1.E+02
1.E+01
1.E+00
1.E-01
1.E-02
1.E-03
A
B
A
M1
V ss
M2
B
V m
A & B = 0 V cc – V t
M1
M2
LowV t , 110 °C
M2
HighVt , 30 °C
M1
V cc
0 0.2 0.4 0.6 0.8 1
Intermediate Node Voltage (V)
C j