U. Glaeser

The performance of Type 3 equalizers consisting of a T spaced FIR filter with only a Nyquist antialiasing
CTF was also examined. Also, the Type 3 equalizer cannot approach the performance of a system
whose CTF is involved in equalization and is optimized. Therefore, to make a valid comparison between
FIR and CTF equalizers, one must include a reasonably optimum CTF prior to the FIR.
It has been demonstrated that a wide variety of optimized CTF + FIR equalizers can perform within
0.25 dB of the quantized system using the oversampled T/5 equalizer. As this 0.25 dB includes performance
losses due to AGC and timing recovery, there is very little space left for improved equalization with any
other equalizer architecture.
Adaptive Timing Recovery
In storage systems such as PRML magnetic recording channels a clock is used to sample the analog
waveform to provide discrete samples to symbol-by-symbol (s/s) and sequence (Viterbi) detectors.
Improper synchronization of these discrete samples with respect to those expected by the detectors
for a given partial response will degrade the eventual BER of the system. The goal of adaptive timing
recovery is to produce samples for the s/s or sequence detector, which are at the desired sampling
instances for the partial response being used. In this subsection, the basics of timing recovery as well
as commonly used algorithms for timing recovery in magnetic recording channels are reviewed. Two
classes of timing recovery algorithms are presented: symbol rate VCO-based and interpolation-based
algorithms. After a discussion of the trade-offs between these two types of algorithms, the focus will
be on the traditional symbol rate VCO algorithms for the rest of the discussion. One of these timing
recovery algorithms from first principles will be derived. An analytical framework for comparing the
performance of such algorithms using timing loop noise induced output jitter as the performance
criterion is provided. Finally, quantitative comparative performance data for some of these algorithms
based on the jitter analysis as well as simulations, which measure timing loop jitter and BER, is
provided.
Timing Recovery Basics
Symbol Rate VCO versus Interpolative Timing Recovery
Timing recovery schemes, which have been considered for magnetic recording channels, can be broadly
classified into two groups: traditional symbol rate VCO-based schemes and interpolative schemes, [21,22],
which sample slightly above the symbol rate. The key difference between the schemes is that the symbol
rate VCO scheme adapts or adjusts the phase and frequency of the sampling clock to produce the desired
samples whereas interpolative timing recovery samples the analog waveform using a uniformly sampled
clock to produce samples from which the desired samples are interpolated.
Figure 34.22 shows high-level block diagrams of both approaches. Let us describe the VCO-based
approach first. For the sake of the discussion the VCO approach is shown with an analog FIR equalizer.
Consequently the sampling occurs at the input of the FIR equalizer. The noisy equalized output y(k)
must be used to detect the timing error present in these samples. This is done using a phase detector.
The phase detector transforms an amplitude error in the samples to ∆(k), which is related to the desired
change in the sampling phase. The phase detector output is also called the timing gradient.
The phase detector may require the use of the noisy equalized samples y(k) or other signals derived
from it. The other signals may be the preliminary or tentative decisions s, decision directed
estimates of y(k), which are or other signals. These auxiliary signals are generated by the block
labeled “Signal Generation for Phase Detector.” The y(k)s are used to generate preliminary (tentative)
decisions and an error signal e(k), and a decision directed estimate of the ideal equalized sample
value, .
The phase detector output is filtered by a loop filter T(z). The loop filter T(z) is usually a second order
DPLL with an additional delay term z −L d
, which models any latency through the timing loop. Such latency
arises from the group delay of the FIR, computations in the DPLL, calculating the signals needed by the
phase detector, etc. The filtered phase detector output is the input to a VCO, which causes the actual
ˆ( k)
yˆ ( k)
dˆ ( k)
yˆ ( k)
© 2002 by CRC Press LLC