U. Glaeser

4. Koller, J. G. and Athas, W. C., Adiabatic switching, low energy computing, and the physics of storing
and erasing information, in Proc. Workshop on Physics and Computation, PhysComp ’92, Dallas,
1992.
5. Athas, W. C., Energy-recovery CMOS, in Low Power Design Methodologies, Rabaey, J. M. and Pedram,
M., Eds., Kluwer Academic Publishers, Boston, MA, 1996, 65.
6. Watkins, B. G., A low-power multiphase circuit technique, IEEE J. of Solid-State Circuits, 2, 213, 1967.
7. Seitz, C. L., Frey, A. H., Mattisson, S., Rabin, S. D., Speck, D. A., and van de Snepscheut, J. L. A.,
Hot-clock NMOS, in Proc. Chapel Hill Conference on VLSI, Chapel Hill, 1985, 1.
8. Svensson, L. J., Adiabatic switching, in Low Power Digital CMOS Design, Chandrakasan A. P. and
Brodersen, R. W., Eds., Kluwer Academic Publishers, Boston, MA, 1995, 181.
9. Younis, S. G. and Knight, T. F., Asymptotically zero energy split-level charge recovery logic, in Proc.
Int. Workshop on Low-Power Design, Napa Valley, 1994, 177.
10. Denker, J. S., A review of adiabatic computing, in Proc. Symp. on Low Power Electronics, San Diego,
1994, 94.
11. Kramer, A., Denker, J. S., Avery, S. C., Dickinson, A. G., and Wik, T. R., Adiabatic computing with
the 2N-2N2D logic family, in Proc. Int. Workshop on Low-Power Design, Napa Valley, 1994, 189.
12. Gabara, T., Pulsed power supply CMOS⎯PPS CMOS, in Proc. Symp. on Low Power Electronics, San
Diego, 1994, 98.
13. De, V. K. and Meind, J. D., A dynamic energy recycling logic family for ultra-low-power gigascale
integration (GSI), in Proc. Int. Symp. of Low Power Electronics and Design, Monterey, 1996, 371.
14. Moon, Y. and Jeon, D.-K., An efficient charge recovery logic circuit, IEEE J. of Solid-State Circuits,
31, 514, 1996.
15. Maksimovic, D., Oklobdzija, V. G., Nicolic, B., and Current, K. W., Clocked CMOS adiabatic logic
with integrated single-phase power-clock supply: experimental results, in Proc. Int. Symp. of Low
Power Electronics and Design, Monterey, 1997, 323.
16. Kim, S. and Papaefthymiou, M. C., Single-phase source-coupled adiabatic logic, in Proc. Int. Symp.
of Low Power Electronics and Design, San Diego, 1999, 97.
17. Younis, S. G. and Knight, T. F., Non-dissipative rail drivers for adiabatic circuits, in Proc. Conference
on Advanced Research in VLSI, Chapel Hill, 1995, 404.
18. Athas, W. C., Svensson, L. J., and Tzartzanis, N., A resonant signal driver for two-phase, almost
nonoverlapping clocks, in Proc. Int. Symp. on Circuits and Systems, Atlanta, 1996, 129.
19. Yuan, J. and Svensson, C., High-speed CMOS circuit technique, IEEE J. of Solid-State Circuits, 24,
62, 1989.
20. Glasser, L. A. and Dobberpuhl, D. W., The Design and Analysis of VLSI Circuits, Addison-Wesley,
Reading, MA, 1985.
21. Tzartzanis, N. and Athas, W. C., Clock-powered logic for a 50 MHz low-power datapath, in Proc.
Int. Solid-State Circuits Conference, San Francisco, 1997, 338.
22. Tzartzanis, N., Energy-Recovery Techniques for CMOS Microprocessor Design, Ph.D. Dissertation,
University of Southern California, Los Angeles, 1998.
23. Tzartzanis, N. and Athas, W. C., Clock-powered CMOS: a hybrid adiabatic logic style for energyefficient
computing, in Proc. Conference on Advanced Research in VLSI, Atlanta, 1999, 137.
24. Athas, W. C. and Tzartzanis, N., Energy recovery for low-power CMOS, in Proc. Conference on
Advanced Research in VLSI, Chapel Hill, 1995, 415.
25. Veendrick, H. J. M., Short-circuit dissipation of static CMOS circuitry and its impact on the design
of buffer circuits, IEEE J. of Solid-State Circuits, 19, 468, 1984.
26. Usami, K. and Horowitz, M. A., Clustered voltage scaling technique for low-power design, in Proc.
Int. Symp. on Low-Power Design, Dana Point, 1995, 3.
27. Hall, J. S., An electroid switching model for reversible computer architectures, in Proc. Workshop on
Physics and Computation, PhysComp ’92, Dallas, 1992.
28. Athas, W. C., Tzartzanis, N., Svensson, L. J., and Peterson, L., A low-power microprocessor based
on resonant energy, IEEE J. of Solid-State Circuits, 32, 1693, 1997.
© 2002 by CRC Press LLC