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FIGURE 15.17 Floating-point datapath clocking of Alpha 21264 [36].<br />

References<br />

1. Kuroda T. and Sakurai T., Overview of low-power ULSI circuit techniques, IEICE Trans. Electronics,<br />

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inverter delay and other formulas, IEEE J. Solid-State Circuits, vol. 25, no. 2, p. 584, 1990.<br />

3. Kitsukawa G., et al., 256 Mb DRAM technologies for file applications, Int. Solid-State Circuits<br />

Conference Dig. Tech. Papers, p. 48, 1993.<br />

4. Horiguchi M., Sakata T., and Itoh K., Switched-source-impedance CMOS circuit for low standby<br />

subthreshold current giga-scale LSI’s, Symposium on VLSI Circuits Dig. Tech. Papers, p. 47, 1993.<br />

5. Mutoh S., et al., 1 V high-speed digital circuit technology with 0.5 µm multithreshold CMOS, Proc.<br />

IEEE Int. ASIC Conference and Exhibit, p. 186, 1993.<br />

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CMOS, IEEE J. Solid-State Circuits, vol. 30, no. 8, p. 847, 1995.<br />

7. Shigematsu S., et al., A 1 V high-speed MTCMOS circuit scheme for power-down application circuits,<br />

IEEE J. Solid-State Circuits, vol. 32, no. 6, p. 861, 1997.<br />

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for sub-1V MT-CMOS LSIs, Symposium on VLSI Circuits Dig. Tech. Papers, p. 14, 1996.<br />

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© 2002 by CRC Press LLC<br />

CLK_1A_H<br />

CLK_1B_H<br />

CLK_2A_H<br />

CLK_2B_H<br />

B-LATCH<br />

B-LATCH<br />

B-LATCH<br />

B-LATCH<br />

ENABLE<br />

CLK<br />

MUL CLOCKS<br />

INT CLOCKS<br />

ADD CLOCKS<br />

DIV CLOCKS<br />

SQRT CLOCKS<br />

MUL CLK ENABLE<br />

GLOBAL CLOCK<br />

INT CLK ENABLE<br />

ADD CLK ENABLE<br />

DIV CLK ENABLE<br />

SQRT CLK ENABLE

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