U. Glaeser

This method, however, lacks the applicability to general pass-transistor networks and is also inefficient
because the resulting networks have a very large number of gates.
Delay fault testing [17–21] based on gate or path delay fault models has recently emerged as the
potentially most powerful method for functional testing. In order to achieve a high fault coverage, delay
fault testing requires a detailed timing characterization of the circuit elements. Although this is usually
satisfied for gate-level ATPG based on logic primitives, it is difficult to compute timing properties in a
full-custom design style employing complex gates, transistor networks, and bidirectional switch-level
macros. If no explicit timing information is available, a transition fault model [22] is the most convenient
choice. Such a model checks for possible high-low and low-high transitions of all internal circuit nodes
at gate-level. The system clock then sets the timing limit for transitions.
Recently, the detection of defects beyond functional faults by methods such as built-in overcurrent
measurements (Iddq-testing) [23,24] has received considerable attention. Despite their potential coverage
of transistor faults and bridging faults, these methods are static by nature and therefore they are a complement
to, instead of a replacement for, dynamic testing.
The work introduced here is aimed at the generation of efficient test sets for conventional voltagebased
tests as well as for Iddq tests. The method is based on the transition fault model and on available
structural information at transistor-level and gate-level. Our software also supports various other fault
models. The basic approach relies on relatively few but efficient modifications to the FAN algorithm
in combination with adapted local switch-level test generation. The advantage over other approaches
is that switch-level structures are only addressed where truly necessary, and fault propagation is essentially
handled at gate-level. Test sets are kept short by using robust multipattern sequences where
possible.
A sequential test pattern generation approach is presented in the second part of this paper. It is based
on the new FOGBUSTER-algorithm. As opposed to the BACK-algorithm [25], which was built on basic
theoretical work [26,27], FOGBUSTER uses a forward propagation and backward justification technique,
which is in general more efficient than the exclusive reverse time processing BACK uses.
The advantage of all these test pattern generators over simulation-based approaches [28,29], which are
generally much faster than these techniques, is that they are complete, i.e., for any given testable fault a
test pattern is generated assuming sufficient time.
The overall approach is summarized in Table 45.1. Although MILEF (mixed-level FAN) is able to
generate test patterns for combinational circuits using a modified FAN-algorithm, SEMILET can generate
test patterns for synchronous sequential circuits using the FOGBUSTER-algorithm.
The rest of this chapter is organized as follows: The first part (Section 45.2) describes the mixed-level
ATPG approach for combinational logic. The second part is devoted to sequential ATPG (Section 45.3).
Results for the ISCAS ’85 (combinational) and the ISCAS ’89 (sequential) benchmark circuits are presented
and compared to other approaches. The chapter ends with a summary (Section 45.4).
© 2002 by CRC Press LLC
TABLE 45.1 The Relation between Test Generation Approaches
ATPG Tool MILEF SEMILET
Circuit behavior Combinational circuits or full
scan circuits
Synchronous sequential circuits
Algorithm Modified FAN FOGBUSTER
Test generator for embedded
switch-level macros
CTEST CTEST
Voltage-based fault models Stuck-at
Stuck-open
Transition
Stuck-at
Current-based fault models Stuck-at
Stuck-at
Stuck-on
Stuck-on