U. Glaeser

FIGURE 37.5 Achilles 3-D stack. Each small PCB contains one FPGA: connections are made by cabling between
the connectors visible on each small PCB.
• Database and text searching
• Compression
• Signal processing
It is generally straightforward to transfer an algorithm from a general-purpose processor to reconfigurable
hardware; synthesizers which convert VHDL or Verilog models into the bit streams necessary to program
an FPGA-based system are available and efficient; however, a successful transfer must provide a solution
which is more efficient, by some criterion, than the same algorithm running on fast commodity general-
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purpose processors. Reconfigurable hardware generally runs slower, consumes more power, and costs
more than commodity processors. This remains true at most points in the performance spectrum. At
the low performance end, small processors, e.g., Motorola’s HC11 series, are available at very low cost
and very low power consumption and will thus perform simple control and data processing tasks
effectively. Although a modern FPGA may outperform the relatively slow processors available at the low
end of the performance spectrum, there are a host of general-purpose embedded processors, e.g., the
PowerPC-based devices, which will provide the additional processing power while still consuming less
power and costing less than an FPGA. At the high performance end of the spectrum, the internal clock
speeds of FPGAs lag behind those of commodity processors and thus their sequential processing
capability does not match that of, for example, a state-of-the-art Pentium or SPARC processor; however,
although it is clear that reconfigurable hardware will not provide efficient solutions for all problems,
there are areas in which it is extremely efficient.
The general characteristics of successful applications are
(a) Sufficient parallelism: The processing algorithm must have sufficient inherent parallelism to allow
multiple processing pipelines to be created. This parallelism can be either direct or pipelined.
(b) Low storage requirements: Early FPGAs provided very few bits of memory—the flip-flops in logic
blocks were an expensive way to provide memory. Later FPGAs have addressed this problem by
allowing the configuration bits to be used as lookup tables and thus provides tens of bits per logic
block. The newest generation of FPGAs provide blocks of dedicated memory but capacities are
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However, Tsu et al., argue that there is no inherent reason why an FPGA should be slower [16].
© 2002 by CRC Press LLC