U. Glaeser

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FIGURE 2.91 History effects.
stages have lower V th than do the n-MOSFETs of the even-numbered stages. The reason for this characteristic
is that the odd-stage n-MOSFETs have a high body potential due to impact ionization. This
imbalance in V th in the inverter chain results in the longer pulse width after passing through the chain.
The time constant for the charging and discharging is relatively long (1 ms or longer, for example), so
the shorter the pulse period becomes, the smaller the extension of the pulse width becomes. IBM
investigated the effect of changes in the dynamic body potential during the operation of this kind of
circuit on various logic gate circuit delay times and found that the maximum change in the delay time
was about 8%. Although this variation in delay times is increased by the use of PD-SOI devices, various
factors also produce variation when bulk Si devices are used. For example, there is a variation in delay
time of 15–20% due to changes in line width within the chip that result from the fabrication process, a
variation of 10–20% due to a 10% fluctuation in the on-chip supply voltage, and a variation of between
15% and 20% from the effect of temperature changes (25–85°C). Compared with these, the 8% change
due to the floating body is small and permissible in the design [15].
FD-SOI Application to Low-Power, Mixed-Signal LSI
Features of FD-SOI Device
As we have already seen in the comparisons of Fig. 2.78 and Table 2.5, in addition to the SOI device
features, the special features of the FD-SOI device include a steep subthreshold characteristic and small
dynamic instabilities such as changes in Vth during circuit operation due to the floating body effect. In
particular, the former is an important characteristic with respect to low-voltage applications. The subthreshold
characteristics of FD-SOI devices and bulk Si devices are compared in Fig. 2.92. Taking the
subthreshold characteristic to be the drain current–gate voltage characteristic in the region of gate voltages
below the Vth, the drain current increases exponentially with respect to the gate voltage (Vg). The steeper
this characteristic is, the smaller can be made the drain leak current when Vg = 0, which is to say the
standby leak at the time the LSI was made even if Vth is set to a small value. An effective way to realize
low-power LSI chips is to lower the voltage. In order to obtain circuit speed performance at low-voltages,
it is necessary to set Vth to a low value. On the other hand, because there is a trade-off between reduction
of the Vth and the standby leak current, we can see that the characteristic described above is important
[7,22]. As a criterion for steepness, the subthreshold coefficient (S) is defined as the change in the gate
voltage that is required to change the drain current in the subthreshold region by a factor of 10. This
coefficient corresponds to the proportion of the change in channel surface potential with respect to the
change in gate voltage. For the FD type structure, the body region is fully depleted, so the channel
© 2002 by CRC Press LLC
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PD-SOI n-MOSFETs
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f =10 Hz
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f =2 MHz
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TIME (ns)