U. Glaeser

FIGURE 21.8 Potential E-R latch for precharged logic.
FIGURE 21.9 E-R latches used with precharged logic ([28] © 1997 IEEE).
the timing diagram of Fig. 21.7(a). Also note that the point Vdd − Vth is chosen assuming that Vdd is higher
than Vϕ, which may not be the case.
One solution to this problem is to set Vdd to 2Vth, which would impose restrictions on the system’s
operating voltage, and hence on its maximum frequency. Another solution is to precharge with an nFET
driven by the other phase (Fig. 21.7(b)). This would require Vϕ to swing between 0 V and Vdd + Vth; otherwise, the inverter would experience a short-circuit current. A keeper pFET driven by aout (shown
with dashed lines in Fig. 21.7(b) can restore the voltage level of the precharged gate if necessary. The
latter solution is more attractive because, despite the restrictions between the supply voltage Vdd and the
clock voltage swing Vϕ, it provides a wider range of operating points. Moreover, it dictates that the clockpowered
nodes be in higher energy levels than the dc-powered nodes, but the effect is mitigated when
dissipation is considered because energy is recovered from the high-energy, clock-powered nodes.
If Vϕ swings from 0 V to Vdd + Vth, then a latch-stage that can be used for the E-R latch is the 3-transistor
dynamic latch (Fig. 21.8). If necessary, the dynamic node DinL can be staticized with an inverter. Alternatively,
a keeper pFET driven by DinL can restore the voltage at node DinL. Figure 21.9 shows how an E-R latch drives a precharged gate and how the output of the gate is stored in
an E-R latch. The gate precharges on ϕ1 and evaluates on ϕ2. Although for simplicity Fig. 21.9 shows a single
gate, precharged gates can be arranged in domino style; the outputs of the final stage are stored in E-R latches.
The precharged gates and the E-R latch inverters are powered from the same dc supply with voltage Vdd. Pass-Transistor Logic
The E-R latch design used with precharged logic (Fig. 21.8) can operate with pass-transistor logic as well
(Fig. 21.10). As in precharged logic, the magnitude of clock voltage swing Vϕ is equal to Vdd + Vth. Passtransistor
gates are driven by clock-powered signals. Transistor chains can be driven either by clockpowered
signals (i.e., signal wo in Fig. 21.10) or by dc-powered signals. When transistor chains are driven
by clock-powered signals, the output of the first transistor (signal ui in Fig. 21.10) is a dc-level signal,
due to the threshold voltage drop of the pass transistor. Therefore, dc-level signals are steered through
transistor chains. The higher voltage swing of the clock-powered signals allows the dc-level signals to be
passed at their full swing. Furthermore, some energy along the transistor-chain path can be recovered if
the path is driven by a clock-powered signal; however, for typical pass-transistor gate configurations,
HSPICE simulations indicate that most of the injected energy would be trapped in the path.
© 2002 by CRC Press LLC
x i
ϕ 1
E-R Latch
ϕL Din D I
inL 2
M4 D I
inL 1
the
V
boot
iso
node
(bn)
M1 Latch Stage Clocked-Buffer Stage
V iso
ϕ 2
x o∧ϕ 2
Vdd ϕ1
Precharged
Gate
y i
ϕ 2
E-R Latch
ϕ D
M2 Dout M 3
V iso
ϕ1
y o∧ϕ 1