U. Glaeser

FIGURE 2.39 Reduce operation and reduced BDD.
FIGURE 2.40 BDD size dependency on variable ordering for Out = AB + CD + EF.
from the property of a BDD called canonicity [21]. Canonicity means that after reduce operation that
removes isomorphic sub-graphs, as shown in Fig. 2.39(a–c), the final BDD is always identical for the
same logic function and the same variable ordering, even if the initial BDDs are different. Here, variable
ordering means the order of the input variables in the BDD construction. A BDD for which the redundant
sub-graphs have been removed by the reduce operation is called a reduced BDD (RBDD) or reduced
ordered BDD (ROBDD). In this chapter, a BDD is assumed to be a ROBDD, unless otherwise stated.
Because of this canonicity property of BDDs, the synthesized PTL is independent of the input HDL
quality and redundancy free. This is one of the most important advantages of PTL synthesized from a
BDD, compared with CMOS logic synthesis, in which the result depends on the quality of the input HDL
description. The canonicity of BDDs also plays an important role in other fields in logic synthesis such
as formal verification of logic functions [21].
Variable Ordering of BDDs
As described in the previous section, the BDD has various superior characteristics for PTL synthesis.
However, it has a drawback in that its size strongly depends on the input variable ordering. In PTL
synthesis, the size of the BDD is directly reflected by the synthesized result. Therefore, finding the variable
ordering that generates the minimum-size BDD is important. For example, Fig. 2.40 compares the BDDs
for the logic function Out = AB + CD + EF for two different variable orders: (a) A → B → C → D →
E → F, and (b) A → C → E → B → D → F. As shown in the figure, for case (a), the node count of the
BDD is 6. On the other hand, 14 nodes are required for the same logic function in case (b). In general,
an inefficient variable order can increase the size of a BDD by an order of magnitude.
However, the problem of finding appropriate variable ordering for arbitrary logic functions is well
known to be an NP-complete problem [23]. For a logic function with a small number of inputs, it is
possible to examine all combinations of variable ordering with a practical time. However, such a method
© 2002 by CRC Press LLC
B
C C
Out
A
0 1 0 1
isomorphic subgraph
(a) Original
E
C
F
Out
A
D
B
1 0
B
reduce
6 nodes
Out
Out
A A
elimination
B B C
C
0 1
(b) After reduction
1 0 0 1 1 0
(a) A→B→C→D→E→F (b) A→C→E→B→D→F
C
E E
Out
A
C
E E
B B B B
0 1 0
1
D
F
D
B
(c) Reduced BDD
14 nodes