U. Glaeser

FIGURE 42.4
coordinate rotation (CORDIC) algorithm. These two approaches are depicted in Fig. 42.4. The two
metrics for measuring the performance of a DDFS are the minimum frequency resolution ∆f
and the
spurious free dynamic range (SFDR). The frequency resolution can be improved by increasing the wordlength
used in the accumulator, while the SFDR is affected by the wordlengths in both the accumulator as well
as the sine/cosine generation block.
One of the main challenges in the development of the table lookup DDFS has been to limit the size
of the sine/cosine table. This has been accomplished through two steps [9]. First, by exploiting the
symmetry of the sine and cosine functions it is only necessary to store β of the period of a sine wave and
derive the remainder of the period through manipulation of the saved portion. Second, the number of
bits per entry can be reduced by dividing the sine table between a coarse ROM and a fine ROM with the
final result obtained after simple post-processing of the values. Combining these two techniques can
result in the reduction of the sine tables by an order of magnitude or better.
In the CORDIC algorithm, Fig. 42.4, sine and cosine of the argument are calculated using a cascade of
k
k
stages, each of which rotates its input complex vector by δ/
2 ( δ = π/
2) if the kth
bit of W is 0 and −δ/
2
if the bit is a 1. Thus each stage performs the following matrix operation:
In [10] a simplification of the CORDIC DDFS is presented in which for small θ,
tan( θ)
is simply
approximated by θ.
In [11] a different modification to the CORDIC architecture is proposed that will
facilitate low-power operation in cases where a sustained frequency is to be generated. This is achieved
by calculating the necessary angle of rotation for each sampling clock period, and dedicating a single
rotation stage in a feedback configuration to contiually rotate the phasor through the desired angle.
Decimate/Interpolate Filters
Variable rate interpolation and decimation filters play a very important role in the development of highly
flexible and self contained all-digital receivers. As previously mentioned, they are the critical element of
all digital timing recovery loops as well as systems capable of operating at a host of user defined symbol
rates. Additionally, digital resampling allows the ASIC designer to ensure that the clock frequency at all
portions of the circuit are the minimum that they need to be to properly represent the signals. This could
have significant impact on the size and power consumption of the resulting ASIC since power scales with
the clock frequency and the square of the supply voltage. Thus, for a given circuit with a critical path of
say τ seconds, if the data rate into the block is lowered by a factor K,
then the frequency dependent portion
of the dissipated power is also scaled by the same factor; however, additional power savings can be achieved
by noting that the block now has Kτ
seconds to complete its task. Because the speed of a digital circuit is
proportional to the supply voltage, we can reduce the supply voltage and still ensure that the circuit meets
the speed constraints.
© 2002 by CRC Press LLC
W
W
+
+
N bits
Reg
N bits κ
Reg
θ (t)
0
θ(t)
Sin()
Look Up or
Generation
Cos ( βWt)
Sin ( βWt)
Cos ( βWt)
Sin ( βWt)
Two most common DDFS architectures: (a) Table lookup and (b) Coordinate rotation (CORDIC).
xout yout xin yin cosθ – sinθ
1 – tanθ
=
sinθ cosθ
=
cosθ
tanθ 1
(a)
(b)
xin yin