U. Glaeser

FIGURE 18.3
TABLE 18.3
co-processors working in pipeline, i.e., a DCT co-processor based on an instruction set (program memory
based) and a Huffman encoder based on random logic, finite state machines, one has the following results
(Table 18.3, synthesized by Synopsys in 0.25 µ m TSMC process at 2.5 V) 400 images can be compressed
per second with a 13 mA power consumption. At 1.05 V, 400 images can be compressed per second with
a 1 mA power consumption, resulting in quite a large number of 80,000 compressed images per watt
(1000 better than a programmed-based implementation).
Figure 18.3 shows an interesting architecture to save power. For any application there is some control
that is performed by a microcontroller (the best machine to perform control). But in most applications,
there is also a main task to execute such as DSP tasks, convolutions, JPEG, or other tasks. The best
architecture is to design a specific machine (co-processor) to execute such a task. So this task is executed
by the smallest and the most energy efficient machine. Most of the time, both microcontroller and
co-processors are not running in parallel.
Low-Power Memories
Memory organization is very important in systems on a chip. Generally, memories consume most of the
power. So it comes immediately that memories have to be designed hierarchically. No memory technology
can simultaneously maximize speed and capacity at lowest cost and power. Data for immediate use is
stored in expensive registers, in cache memories, and less used data in large memories.
For each application, the choice of the memory architecture is very important. One has to think of
hierarchical, parallel, interleaved, and cache memories (sometimes several levels of cache) to try to find
the best trade-off. The application algorithm has to be analyzed from the data point of view, the organization
of the data arrays, and how to access these structured data.
If a cache memory is used, it is possible, for instance, to minimize the number of cache miss while
using adequate programming as well as a good data organization in the data memory. For instance, in
inner loops of the program manipulating structured data, it is not equivalent to write (1) do i then do j
or (2) do j then do i depending on how the data are located in the data memory.
Proposing a memory-centric view (as opposed to the traditional CPU-centric view) to SoC design has
become quite popular. It is certainly of technological interest. It means, for instance, that the DRAM
memory is integrated on the same single chip; however, it is unclear if this integration inspires any truly
© 2002 by CRC Press LLC
DCT Co-processor
Huffman co-processor
JPEG compression
Frequency and Power Consumption for a JPEG Compressor
No. of Cycles 3.6 per Pixel
3.8 per pixel
3.8 per pixel
Microcontroller and co-processor.
Frequency 100 MHz
130 MHz
100 MHz
Power 110 µ AMHz
20 µ AMHz
130 µ AMHz