U. Glaeser

FIGURE 6.17 A schematic for a bimodal predictor.
“Baddr” is the branch address or PC, which is used to index
the PHT (pattern history table), select the corresponding
two-bit counter, and make a prediction of taken or nottaken.
the fetch block after the branch are still valid and can still be passed on to decode. The second solution
is for the branch predictor to just predict fetch-block successors instead of specific branches. In this case,
the predictor simply predicts whether the next fetch block will be sequential (not-taken) or non-sequential
(taken, in which case the target supplied by the BTAC is used). This is slightly better than the first choice,
because it eliminates the need for pre-decode bits and can fetch past more than one not-taken branch
in a fetch block. It does require the decode stage to identify how each branch in a fetch block was implicitly
predicted. The third solution is for the BTAC and branch predictor to be indexed with the address of
every instruction in the fetch block. Hits in the BTAC indicate which instructions are branches, and only
the corresponding direction predictions are then used. The problem with this approach is that it requires
as many ports into the BTAC and branch-prediction structures as there are instructions in the fetch
block. These are the basic choices, although many variations and improvements have been proposed,
e.g., [24,28–30].
Bimodal Prediction
The simplest dynamic technique, introduced by Smith [17], is to maintain a small, on-chip memory
with a table of saturating counters that is indexed by branch address. The saturating counters—typically
two bits each—simply remember the predominant direction of previous outcomes for that branch. A
schematic for a bimodal predictor appears in Fig. 6.17. As mentioned, the table—usually called the pattern
history table or PHT—although logically a distinct entity, might actually be implemented as a unified
structure with the BTAC. This prediction scheme goes by different names, often simply “two-bit prediction,”
but recent literature has often referred to it as “bimodal” prediction to distinguish it from other
more sophisticated schemes that also use two-bit saturating counters.
Each time a branch resolves, its corresponding counter is incremented if the branch was taken, and
decremented if not. Incrementing or decrementing has no effect if the counter is already at its maximum
or minimum value, hence the term “saturating” counter and the name “bimodal.” In the simplest case of
a one-bit counter, the only possibilities are values of 0 and 1 and the predictor simply remembers the last
outcome for each branch. In the case of two-bit counters, values of 00 and 01 correspond to strongly nottaken
and weakly not-taken, and values of 10 and 11 corresponding to weakly taken and strongly taken.
Two-bit counters give better performance because they exhibit some hysteresis that makes them less
sensitive to infrequent occurrences of outcomes in the non-dominant direction. A state-transition diagram
for the most common two-bit counter configuration appears in Fig. 6.18. Other configurations [18,31]
are possible, however, for example, regardless of its current state, the counter might reset to 00 on a nottaken
branch.
As an example of how two-bit counters improve over one-bit counters, recall that a loop branch will
normally be taken. When the loop exits, a one-bit counter will only remember that most recent direction
(not taken), even though the predominant direction is “taken.” When this same loop is encountered
again, and the loop branch will once again be taken until the loop exits, the first prediction with a onebit
counter will be “not taken.” A two-bit counter, on the other hand, only changes its state from 11 to
10 upon loop exit, and still predicts taken when it returns to the loop, thus eliminating a misprediction
compared to the one-bit counter.
© 2002 by CRC Press LLC
baddr
PHT
T/NT