U. Glaeser

Dynamic Logic Circuits
The basic idea behind the dynamic logic is to use the capacitive input of the MOSFET to store a charge
and thus remember a logic level for later use. The output decays with time unless it is refreshed periodically
since it is stored in a capacitor. Dynamic logic gates, which are also known as clocked logic gates, are
used to decrease complexity, increase speed, and lower power dissipation.
Figure 2.17 shows the basic structure of a dynamic CMOS logic circuit. The dynamic logic design
eliminates one of the switch networks from a complementary logic circuit, thus reducing the number of
transistors required to realize a logic function by almost 50%. The operation of a dynamic circuit has two
phases: a precharge phase and an evaluation phase depending on the state of the clock signal. When clock
CLK = 0, the PMOS transistor in the circuit is turned ON and the NMOS transistor in the circuit is turned
OFF, and the load capacitance is charged to V DD. This is called the precharge phase. The precharge phase
should be long enough for the load capacitance to completely charge to V DD. During the precharge phase,
since the NMOS transistor is turned OFF, no conducting path exists between V DD and ground, thus
eliminating static current. The precharging phase ends and the evaluation phase begins when the clock
CLK turns 1. Now the PMOS transistor is turned OFF and the NMOS transistor is turned ON. Depending
on the values of the inputs and the composition of the pull-down network, a conditional path may exist
between the output and the ground. If such a path exists, the capacitor discharges and logic low output
© 2002 by CRC Press LLC
(a) (b)
(c)
FIGURE 2.16 (a) CMOS positive-level sensitive D latch and the switch level equivalent circuits for CLK = 0 and
CLK = 1; (b) CMOS positive-edge triggered D flip-flop and the switch level equivalent circuits for CLK = 0 and CLK = 1;
(c) CMOS implementation of the positive-edge triggered D flip-flop.