U. Glaeser

FIGURE 10.51
FIGURE 10.52
Max-timing
Pulsed latches are meant to be used as one per pipeline stage, as mentioned earlier, so the pipeline overhead
is limited to only one latch delay (see Eq. (10.2)). This is half the overhead of a dual-phase, latch-based
design. Furthermore, logic partitioning is similar to a flip-flop-based design, simplifying clock distribution.
Time Borrowing
Although still possible, the amount of time borrowing is greatly reduced when using pulsed latches. From
Eq. (10.14), Tborrow
= TON
− ( Tsetup
+ Tskew).
If TON
is chosen such that TON
= Tsetup
+ Tskew,
then time borrowing
is reduced to zero; however, the clock skew can still be hidden by the latch, i.e., it is not subtracted from
the clock cycle for max-timing.
Min-timing
This is the biggest challenge designers face when using pulsed latches. As shown by Eq. (10.16), the
minimum propagation delay in a latch-based system is given by Tmin
> Thold
− TCKQ
+ TON
+ Tskew.
Ideally,
to minimize min-timing problems, TON
should be as small as possible. However, if it becomes too small,
the borrowing time may become negative (see above), meaning that some of the clock skew gets subtracted
from the cycle time for max-timing. Again, this represent another trade-off that designer must face when
selecting a latching strategy. In general, it is good practice to minimize min-timing at the expense of
max-timing. Although max-timing failures affect the speed distribution of functional parts, min-timing
failures are in most cases fatal.
From a timing analyzer perspective, pulsed latches can be treated as flip-flops. For instance, by redefining
T ′
hold = Thold
+ TON,
min-timing constraints look identical in both cases (see Eqs. (10.16) and
(10.21)). Also, time borrowing in practice is rather limited with pulsed latches, so the same timing tools
and methodology used for analyzing flip-flop based designs can be applied.
Last but not least, it is important to mention that designs need not to adhere to one latch or clocking
style only. For instance, latches and flip-flops can be intermixed in the same design. Or single and dualphase
latches can be combined also, as depicted in Fig. 10.52. Here, pulsed latches are utilized in max
paths in order to minimize the pipeline overhead, while dual-phase latches are used in min paths to
eliminate, or minimize, min-timing problems. In this example, the combination of transparent-high and
transparent-low pulsed latches works as a dual-phase nonoverlapping design. Clearly, such combinations
require a good understanding of the timing constraints of latches and flip-flops not only by designers
but also by the adopted timing tools, to ensure that timing verification of the design is done correctly.
© 2002 by CRC Press LLC
D 1
D 2
Q 1
Q 2
Pulsed latch-based design.
D 1
D 2
Max Path
Min Path
Pulsed latch-based design combining single- and dual-pulsed latches.
D 1 ′
D 2 ′
CK CK
Q 1
Q2 Min Path
Max Path
Min Path
D 1′
D 2 ′
CK CK
CK
Q 1 ′
Q 2 ′
Q 1 ′
Q 2 ′