U. Glaeser

FIGURE 12.6
An example of a simple state machine is shown in Fig. 12.6. The state diagram shows that the state
machine has three states with two inputs and one output that is active only in state B. The state machine
resets to state A. Most FPGAs offer some advantages for Moore type state machines (i.e., output a function
of state only) with one-hot encoding (i.e., one flip-flop per state) since they contain a register-rich
architecture with limited gating logic. One-hot state machines are also less prone to timing problems
and are the default encoding used in many FPGA synthesis tools. Since there are undefined states, a reset
should always be provided to force the state machine into a known state. Most FPGAs automatically clear
all flip-flops at power up. The first step in each model is to declare inputs and outputs. An internal signal,
state, is then declared and used to hold the current state. Note that the actual encoding of the three states
is not specified in VHDL, but it must be specified in the Verilog model. The first VHDL PROCESS and
Verilog ALWAYS block are sensitive to the rising clock edge; so positive edge-triggered flip-flops are
synthesized to hold the state signal. Inside the first PROCESS or ALWAYS block, if a synchronous reset
occurs the state is set to state A. If there is no reset, a CASE statement is used to assign the next value of
state based on the current value of state and the inputs. The new assignments to state will not take effect
© 2002 by CRC Press LLC
VHDL Model of State Machine Verilog Model of State Machine
entity state_mach is
port(clk, reset : in std_logic;
input1, input2 : in std_logic;
Output1 : out std_logic);
end state_mach;
architecture A of state_mach is
type STATE_TYPE is (state_A, state_B, state_C);
signal state: STATE_TYPE;
begin
process (reset, clk)
begin
if reset = '1' then
state