U. Glaeser

FIGURE 10.31 Setup and hold time timing diagrams.
FIGURE 10.32 Relationship between setup, hold, and sampling time.
For a properly designed latch, Tsetup + Thold = Tsampling. In contrast to the setup and hold time, which can be manipulated by the choice of latch design, the
sampling time is an independent parameter, which is determined by technology. Setup and hold times
may have positive or negative values, and can increase or decrease at the expense of one another, but the
sampling time has always a positive value. Figure 10.32 illustrates the relationship between the three
parameters in a timing diagram. Notice the lack of a timing dependency between the trailing edge of D′
and Q′
. This is because this transition happens during the opaque phase of the clock. This suggests that
the hold time does not define the maximum speed of a circuit. This will be discussed more in detail
later on.
Timing Constraints
Most designers tend to think of latches and flip-flops as memory elements, but few will think of traffic
lights as memory elements. However, this is the most appropriate analogy of a latch: the latch being
transparent equals to a green light, being opaque to a red light; the setup time is equivalent to the duration
of the yellow light, and the latency to the time to cross the intersection. The hold time is harder to visualize,
but if the road near the intersection is assumed to be slippery, it may be thought of as the minimum
time after the light turns red that allows a moving vehicle to come to a full stop. Slow and fast signals may
be thought of as slow and fast moving vehicles, respectively. Now, when electrical signals are stopped, i.e.,
© 2002 by CRC Press LLC
CK
Q
D′
Q′
CK
D
Q
D
Q
D
Q
D
Q
TSETUP THOLD Transparent Opaque
CK
Q
Metastable
Combinational Logic
Opaque Transparent
Meets
Setup
Fails
Setup
Meets
Hold
Fails
Hold
D′ Q′
CK
T SETUP T HOLD
TSAMPLING