U. Glaeser

FIGURE 39.47 ManArray architectural elements.
Coprocessor Platform” describes how the ManArray architecture fulfills SoC application requirements, with
focus on the implementation, compiler, and tools. “Performance Evaluation” presents performance results,
and last subsection concludes the chapter section.
The ManArray Thread Coprocessor Architecture
In numerous application environments there is a need to significantly augment the signal processing capabilities
of a MIPS, ARM, or other host processor. In addition, many applications require low power consumption
at very high performance levels to accomplish the tasks of emerging applications, such as wireless
LAN (i.e., 802.11a) for battery-powered Internet devices. The BOPS SoC cores provide streamlined coprocessor
attachment to MIPS, ARM, or other hosts for this purpose. Through selectable parallelism, the
ManArray SoC cores achieve high performance at low clock rates, which minimizes power requirements.
The compiler or programmer can select from packed data, indirect VLIW, PE array SIMD, and multiple
threaded forms of parallelism to provide the best product solution. Further, BOPS provides a complete
solution by providing a comprehensive top-down design methodology for delivering the SoC solutions.
The ManArray processor is an array processor using a sequence processor (SP) array controller and
an array of distributed indirect VLIW processing elements (PEs) (see Fig. 39.47). By varying the number
of PEs on a core, an embedded scalable design is achieved with each core using a single architecture.
This embedded scalability makes it possible to develop multiple products that provide a linear increase
in performance and maintain the same programming model by merely adding array processor elements
as needed by the application. As the processing capability is increased, the memory-to-PE bandwidth is
increased, and the system DMA bandwidth may be increased as well. Embedded scalability drastically
reduces development costs for future products because it allows for a single BOPS software development
kit (SDK) to support a wide range of products.
In addition to the embedded scalability, ManArray cores are configurable in the number and type of
cores included on a chip, instruction subsetting for application optimization, the sizes of each SP’s
instruction memory, the distributed iVLIW memories, the PE/SP data memories, and the I/O buffers,
selectable clock speed, choice of on-chip peripherals, and DMA bus bandwidth. The ManArray cores
provide a lower cost, more optimized signal processing solution than reconfigurable processors designed
using FPGA technology [5]. Multiple ManArray cores provide optimized scalable multiprocessing by
including multiple BOPS cores on an SoC product. These multiple ManArray cores can be organized to
provide data pipeline processing between SP/PE-array cores and the parallelization of sub-application
tasks (thread parallelism) with a centralized host-based control to be described later in this chapter section.
Generally speaking, the ManArray processor combines PEs in clusters that also contain a SP, uniquely
merged into the PE array, and a cluster-switch, Fig. 39.47. The SP provides program control, contains
the instruction and data address generation units, and dispatches instructions to the processor array. In
this manner, the ManArray processor is designed for scalability with a single architecture definition and
a common tool set. The processor and supporting tools are designed to optimize the needs of a SoC
platform by allowing a designer to balance an application’s sequential control requirements with the
application’s inherent data parallelism. This is accomplished by having a scalable architecture that begins
© 2002 by CRC Press LLC
SP
iVLIW
PE0
iVLIW
PE1
Scalable DMA
& Host I/O
CS
iVLIW
PEn
Memory
MIPS, ARM, X86
CS=Cluster Switch