U. Glaeser

translates into only 1% full-chip power savings. This is because only 10% of total power is from synthesized
logic for CPUs such as the one whose power breakdown was shown in Fig. 14.13.
It is pertinent to note that the system power consumption problem also encompasses chipsets, i.e.,
devices such as the memory, I/O, and graphics controllers. These operate at a fraction of the CPU clock
frequency, and large portions of these are well-suited to be implemented as ASICs. Low power synthesis
thus has a much larger impact in this domain.
Transistor Sizing
A large part of high-performance CPUs is typically custom designed. These designs typically involve
manual tweaking of transistors to upsize drivers in critical paths. If too many transistors are upsized
unnecessarily, certain designs can operate on the steep part of a circuit’s power-delay curve. In addition,
the choice of logic family used, e.g., static vs. dynamic logic, can also greatly influence the circuit’s power
consumption. Please see the “Need for Power Estimation Tools” subsection and Fig. 14.6.
Figure 14.14 shows an example of another kind of intelligent tradeoff for power/performance. It shows
the results for a logic block whose seven sub-blocks can either be implemented as PLAs or as synthesized
random logic. Increasing the number of synthesized blocks leads to some increase in delay but for much
larger power savings.
The traditional emphasis on performance often leads to over-design, that is, wasteful for power. An
emphasis on lower power, however, motivates identification of such sources of power wastage. An example
of this is the case where paths that are designed faster than they ultimately need to be. For synthesized
blocks, the synthesis tool can automatically reduce power by downsizing devices in such paths. For
manually designed blocks, on the other hand, downsizing may not always get done. Automated downsizing
tools can thus have a big impact. Transistor width savings (with no delay increase) from the use
of one such tool are shown in Table 14.3. The benefit of such tools is power savings, as well as productivity
enhancement over manual designs.
Many custom designers are now exploring dual-Vt technique to take greater advantage of the transistor
sizing. The main idea here is to use low-Vt transistors in critical paths rather than upsizing high-Vt transistors.
The main issue with this technique is the increase in subthreshold leakage due to low-Vt. So it is
very important to use low-Vt transistor selectively and to optimize their usage to achieve a good balance
between capacitive current and leakage current in order to minimize total current.
Examples of Power Reduction Tools
A few examples of power reduction tools and their features are provided here for reference. This is not
a complete list, but only provides an example of what is available commercially. Low-power CAD is thus
an active area of research.
PowerCompiler
It is a gate-level power optimization tool offered by Synopsys, Inc. It helps in achieving low power by
identifying low power opportunites for clock gating, data-gating, logic restructuring, and downsizing. It
also automatically checks feasibility of many low-power design techniques, such as low-power synthesis,
clock gating, etc. and implements it. It also quantifies power savings.
WattSmith
Wattsmith is an RTL power optimization tool offered by Sequence Design, Inc. It helps in identifying
block level power reduction opportunities. It also does automatic implementation of many design
techniques for low power, to name a few: memory banking, clock gating, etc.
© 2002 by CRC Press LLC
TABLE 14.3 Transistor-Width Savings with a Sizing Tool
Ckt1 Ckt2 Ckt3 Ckt4
No. of elements 4853 1953 18300 19756
Width savings (%) 40.00 42.00 17.00 3.00