U. Glaeser

Min-Timing
In contrast to max-timing, min-timing is not immune to clock skew. Figure 10.43 provides a timing
diagram illustrating this case. With reference to Fig. 10.33, clock CK′ is assumed to arrive late. In order
to insure that gets blocked, it is required that:
D′ 2
After rearranging terms, the min-timing requirement is expressed as
© 2002 by CRC Press LLC
TCKQ + Tmin > TON + Tskew + Thold Tmin > Thold – TCKQ + TON + Tskew (10.15)
(10.16)
Equation (10.16) shows that in addition to T ON, T skew is added now. The clock skew presence makes
the min-timing requirement even more strict than before, yielding a single-phase latch design nearly
useless in practice.
Nonoverlapping Dual-Phase, Latch-Based Design
As pointed out in the preceding subsection, the major drawback of a single-phase, latch-based design is
in its rigorous min-timing requirement. The presence of clock skew makes matters worse. Unless the
transparent period can be made very short, i.e., a narrow pulse, a single-phase, latch-based design is not
very practical. The harsh min-timing requirement of a single-phase design is due to the sending and
receiving latch being both transparent simultaneously, allowing fast signals to race through one or more
pipeline stages. A way to eliminate this problem is to intercept the fast signal with a latch operating on
a complementary clock phase. The resulting scheme, referred to as a dual-phase, latch-based design, is
shown in Fig. 10.44. Because the middle latch operates on a complementary clock, at no point in time
CK
CK′
D 2
Q 2
D 2 ′
Q 2 ′
T CKQ
T ON
Transparent
TSKEW THOLD T MIN
Opaque
FIGURE 10.43 Min-timing diagrams for single-phase, latch-based design under the presence of late clock skew.
Sending Middle
Receiving
Latch Latch Latch
Max Path Max Path
D1 Q1 D1 ′ Q1 ′ D1 ″ Q1 ″
D2 Q2 D2 ′ Q2 ′ D2 ″ Q2 ″
Min Path
Min Path
CK A
One Pipeline Stage
CK B
FIGURE 10.44 Nonoverlapping dual-phase, latch-based design.
CK A