U. Glaeser

A more severe limit on the loop bandwidth beyond a decade below the reference frequency can result
in both PLLs and DLLs if there is considerable delay in the feedback path. The decade limit is based on
the phase detector adding one reference period delay in the feedback path since it only samples clock
edges once per reference cycle. This single reference period delay leads to an effective pole near the
reference frequency. The loop bandwidth must be at least a decade below this pole to not affect stability.
This bandwidth limit can be further reduced if extra delay is added in the feedback path, by an amount
proportional to one plus the number of reference periods additional delay.
DLL/PLL Circuits
Prior sections discussed design issues related to DLL and PLL loop architectures and low output jitter.
With these issues in mind, this section discusses the circuit level implementation issues of the loop
components. These components include the VCDL and VCO, phase detector, charge pump, and loop filter.
VCDLs and VCOs
The VDCL and VCO are the most critical parts of DLL and PLL designs for achieving low output jitter
and good overall performance. Two general types of VCDLs are used with analog control. First, a VDCL
can interpolate between two delays through an analog weighted sum circuit. This approach only leads
to linear control over delay, if the two interpolated delays are relatively close, which restricts the overall
range of the VCDL. Second, a VCDL can be based on an analog delay line composed of identical cascaded
delay elements, each with a delay that is controlled by an analog signal. This approach usually leads to
a wide delay range with nonlinear delay control. A wide delay range is often desired in order to handle
a range of operating frequencies and process and environmental variability. However, nonlinear delay
control can restrict the usable delay range due to undesirable loop dynamics.
Several types of VCOs are used. First, a VCO can be based on an LC tank circuit. This type of oscillator
has very high supply noise rejection and low phase noise output characteristics. However, it usually also
has a restricted tuning range, which makes it impractical for digital ICs. Second, a VCO can be based on
a relaxation oscillator. The frequency in this circuit is typically established by the rate a capacitor can be
charged and discharged over some established voltage range with an adjustable current. This approach
typically requires too much supply headroom to achieve good supply noise rejection and can be extra
sensitive to sudden changes in the supply voltage. Third, and most popular for digital ICs, a VCO can be
based on a phase shift oscillator, also known as a ring oscillator. A ring oscillator is a ring of identical
cascaded delay elements with inverting feedback between the two elements that close the ring. A ring
oscillator can typically generate frequencies over a wide range with linear control over frequency.
The delay elements, also known as buffer stages, used in a delay line or ring oscillator can be singleended,
such that they have only one input and one output and invert the signal, or differential, such they
have two complementary inputs and outputs. Single-ended delay elements typically lead to reduced area
and power, but provide no complementary outputs. Complementary outputs provide twice as many output
signals with phases that span the output period compared to single-ended outputs, and allow a 50% duty
cycle signal to be cleanly generated without dividing the output frequency by two. Differential delay elements
typically have reduced dynamic noise coupling to their outputs and provide complementary outputs.
A number of factors must be considered in the design of the delay elements. The delay of the delay
elements should have a linear dependence on control voltage when used in a VCDL and an inverse linear
dependence on control voltage when used in a VCO. These control relationships will make the VCDL
and VCO control gains constant and independent of the operating frequency, which will lead to operating
frequency independent loop dynamics. The static supply and substrate noise sensitivity should be as
small as possible, ideally less than 1% delay sensitivity per fraction of the total supply voltage change. As
previously discussed, this reduced level of supply sensitivity can be established with current source
isolation.
Figure 10.19 shows a single-ended delay element circuit for an N-well CMOS process. This circuit contains
a PMOS common-source device with a PMOS diode clamp and a simple NMOS current source. The diode
clamp restricts the buffer output swing in order to keep the NMOS current source device in saturation.
© 2002 by CRC Press LLC