U. Glaeser

of the cycle time, the effective parallelism achieved is only N × 0.8. If the clock rate were doubled by
making the pipeline twice as deep, e.g., by inserting one additional latch or flip-flop per stage, then the
pipeline overhead would become 40% of the cycle time, or correspondingly, the achieved parallelism 2
× N × 0.6. So in such a case, a doubling of the clock rate translates into a 50% only increase in performance
(2 × 0.6/0.8 = 1.50). In practice, other architectural factors, some of them mentioned above, would reduce
the performance gain even further.
From the above discussion, it becomes clear that in selecting a latch type and clocking scheme, the
minimization of the pipeline overhead is key to performance; however, as discussed in detail throughout
this chapter section, performance is not the only criterion that designers should follow in making such
a selection. In addition to the pipeline overhead, latch- and flip-flop-based designs are prone to races.
This term refers to fast signals propagating through contiguous pipeline stages within the same clock
cycle, resulting in data corruption. Although this problem does not reflect directly in performance, it is
the nightmare of designers because it is usually fatal. If it appears in silicon, it is extremely hard to debug,
and therefore it is generally detrimental to the design cycle. Furthermore, since most of the design time
is spent on verification, particularly timing verification, a system that is susceptible to races takes longer
to design.
Other design considerations, such as layout area, power dissipation, power-delay product, design robustness,
clock distribution, and timing verification, some of which are discussed in this chapter section, must
also be carefully considered in selecting a particular latching design.
Nomenclature and Symbols
The nomenclature and symbols used throughout this chapter are shown in Fig. 10.27. The polarity of the
clock is indicated with a conventional bubble. The presence of the bubble means the latch is transparentlow
or that the flip-flop samples with the negative edge of clock. Conversely, the lack of the bubble means
the latch is transparent-high, or that the flip-flop samples with the positive edge of clock. The term opaque,
FIGURE 10.27 Symbols used for latches, flip-flops, and pulsed latches.
© 2002 by CRC Press LLC
D
CK
Transparent-High Latch
D
D
CK
CK
Q D
Q
CK
Transparent-Low Latch
Q D
Q
Positive Edge-Triggered Flip-Flop Negative Edge-Triggered Flip-Flop
CK
Q D
Q
Transparent-High Pulsed-Latch Transparent-Low Pulsed-Latch
CK