U. Glaeser

for min-timing because the PLL jitter, a significant component in max-timing, is not part of the clock
skew in this case. From a max-timing perspective, Table 10.8 shows that pulsed latches have the minimum
pipeline overhead, the winner being the pulsed transmission gate. The unbuffered transmission gate latch
is a close second. But as pointed out earlier, unbuffered transmission gates are rarely allowed in practice.
In the flip-flop group, SDFF is the best, while the buffered master-slave flip-flop is the worst. Merging a
logic gate inside the latch or flip-flop may result in additional 5% or more reduction in the pipeline
overhead, depending on the relative complexity of the logic function. Precharged designs such as SDFF
or the sense-amplifier flip-flop are best suited to incorporate logic efficiently. From a min-timing perspective,
pulsed latches with externally generated pulses are the worst, while the buffered master-slave
flip-flop is the best. If the pulse is embedded in the circuit (like in SDFF or HLFF), min-timing requirements
are more relaxed. It should be noticed that because of manufacturing tolerances, the minimum
delay requirement is usually larger than what Table 10.8 (fifth column) suggests. One or two additional
gate delays is in general sufficient to provide enough margin to the design.
Although pulsed latches are the best for max-timing, designers must keep in mind that max-timing
is not the only criterion used when selecting a latching style. The longer hold time of pulsed latches may
result in too many race conditions, forcing designers to spend a great deal of time in min-timing
verification and min-timing fixing, which could otherwise be devoted to max-timing optimization. Ease
of timing verification is also of great importance, especially in an industry where a simple and easily
understood methodology translates into shorter design cycles. With the advancement of design automation,
min-timing fixing (i.e., buffer insertion) should not be a big obstacle to using pulsed latches. Finally,
notice that the selection of a latching technique can affect the cycle time of a design by 10–20%. It is important
that designers look into all design trade-offs discussed throughout this chapter section in making the right
selection of the latching scheme.
For a similar analysis of some of the designs included in this section but based on actual transistor
sizing and SPICE simulation, including a power-delay analysis, the reader is referred to [26].
Scan Chain Design
The previous sub-section covered the design of latches and flip-flops and presented a performance analysis
of each of the circuits. In practice, however, these circuits are rarely implemented as shown. This is
because in many cases, to improve testability, a widely accepted practice is to add scan circuitry to the
design. The addition of scan circuitry alters both the circuit topology and the performance of the design.
The design of scannable latches and flip-flops is the subject of this sub-section.
As mentioned previously, a widely accepted industrial practice to efficiently test and debug sequential
circuits is the use of scan design techniques. In a scan-based design, some or all of the latches or flip-flops
in a circuit are linked into a single or multiple scan chains. This
allows data to be serially shifted into and out of the scan chain, greatly
enhancing controllability and observability of internal nodes in the
SE
design. After the circuit has been tested, the scan mechanism is
Data
disabled and the latches of flip-flops operate independently of one
Scan Q
another. So a scannable latch or flip-flop must operate in two modes:
a scan mode, where the circuit samples the scan input, and a data
CK
mode, where the circuit samples the data input. Conceptually, this
may be implemented as a 2:1 multiplexor inserted in the front of the
FIGURE 10.70 A scannable latch.
latch, as suggested in Fig. 10.70. A control signal SE selects the scan
input if asserted (i.e., scan mode) or the data input otherwise.
A straightforward implementation of the scan design of Fig. 10.70 consists of adding, or merging, a 2to-1
multiplexor to the latch. Unfortunately, this would result in higher pipelining overhead because of
the additional multiplexor delay, even when the circuit operates in data mode, or would limit the
embedding of additional logic. It becomes apparent that a scan design should affect as little as possible
the timing characteristic of the latch or flip-flop when in data mode, specifically its latency and hold
time. In addition, it is imperative that the scan design be robust. A defective scan chain will prevent data
© 2002 by CRC Press LLC