U. Glaeser

structures are a powerful solution in the quest for higher LSI performance, lower operating voltage, and
lower power consumption.
Higher Quality and Lower Cost for the SOI Substrate
Against the backdrop of the recognition of SOI CMOS as a key technology for logic LSI of higher
performance and lower power consumption, the fact that SOI substrates based on Si substrates have
higher quality and lower cost are extremely important. A thin-film SOI substrate that has a surface layer
of Si that is less than 0.1 µm thick serves as the substrate for forming the fine CMOS devices of a logic
LSI chip. In addition, various factors of substrate quality, including the quality of the SOI layer, which
affects the reliability of the gate oxide layer and the standby leak current, the uniformity of thickness
of the SOI layer and the buried oxide layer and controllability in the production process, roughness of
the SOI surface, the characteristics of the boundary between the buried oxide layer and the SOI layer,
whether or not there are pinholes in the buried oxide layer, and the breakdown voltage, must be cleared
[8,9]. Furthermore, for the production of SOI CMOS with the same production line, as is used for
CMOS on bulk Si substrate, the absence of metal contamination and a metal contamination gettering
capability are needed. Also, adaptability for mass production, cost reduction, and larger wafer diameters
must be considered. From this point of view, remarkable progress has been achieved in thin-film SOI
substrates for fine CMOS over these past several years. In particular, the SOI substrates that have
attracted attention are broadly classified into SIMOX (separation by implanted oxygen) substrates and
wafer bonding (WB) substrates, as shown in Fig. 2.84. A SIMOX substrate is formed by oxygen ion
implantation and high-temperature annealing. Wafer bonding substrates, on the other hand, are made
by bonding together a Si substrate on which an oxide layer is formed, which is called a device wafer
(DW) because the devices are formed on it, and another substrate, called the handle wafer (HW), and
then thinning down the DW from the surface so as to create an SOI layer of the desired thickness. For
fine CMOS, a thin SOI layer of less than 0.1 µm must be fabricated to a layer thickness accuracy of
within ±5–10%. Because that accuracy is difficult to achieve with simple grinding or polishing technology,
various methods are being studied. Of those, two methods that are attracting attention are ELTRAN
(epitaxial layer transfer) [10] and UNIBOND [11]. ELTRAN involves the use of a porous Si layer formed
by anodizing and a Si epitaxial layer to form the separation layer of the DW and HW; the UNIBOND
substrate uses hydrogen ion implantation in the formation of the peel-off layer. It has already been
demonstrated that the application of these SOI substrates to 300 mm wafers and mass production is
technologically feasible, and because this is also considered to be important from the viewpoint of
application to logic LSI chips, which are a typical representative of MPUs, an overview of the technology
and issues is presented in the next section.
FIGURE 2.84 SOI material technologies for production.
© 2002 by CRC Press LLC
SIMOX
Separation by
IMplanted OXygen
WB
Wafer
Bonding
BESOI
Bond and
Etchback SOI
UNIBOND
Low-Dose
High-Dose
ITOX-SIMOX
Internal Thermal
OXidation
ELTRAN
Epitaxial Layer
TRANsfer