U. Glaeser

As is the case with sizing and topologies for performance, complexity in the analysis and optimization
for robustness and reliability can be controlled through the generation of rather simple guidelines in
sizing, wire length versus spacings, keeper size ratios, etc. In the case of reliability and robustness, however,
verification that noise criteria are met is critical.
13.3 Logic Design Implications
As the technology-independent (FO4-based) cycle time shrinks, and signal distribution and clock and
latch overhead shrink less quickly, the arithmetic and logic design must be more efficient. Linear depth
arithmetic and logic structures quickly become impractical. Linear carry ripple addition, even on small
group size, must be replaced with logarithmic carry-lookahead structures. Multiple arithmetic computations
with a late selection, for example compound addition, may become necessary. In critical macros,
additional logic may need to be introduced to avoid waiting for external select signals. For example, the
carry-generation logic from a floating-point adder needed to be reproduced within the leading-zeroanticipator
of a high-frequency, floating-point unit to avoid waiting for the sign of the add to be formed
and delivered from the floating-point adder. 24
Traditionally sequential events may need to be performed in parallel. For instance, to compute condition
codes, rather than waiting for the result of the ALU operation and using additional levels of logic
to form the condition codes, a parallel condition code generation unit, which formed the condition codes
directly from the ALU input operands faster than the ALU result was required. 25 Sum-addressed caches
have also been used to replace the sequential effective-address addition followed by cache access with a
carry-free addition as part of the cache decoder. 26,27 Of more ubiquitous application, merging of logic
with the latch is important as cycle times shrink. With increased pressure on cycle time, the latches and
clocked circuits need a low skew and low jitter clock. Low jitter clock generation and low skew distribution
require significant design, wiring, and power resource. 28,29
13.4 Variability and Uncertainty
The wires and devices, which are actually fabricated in a design, may differ significantly from the nominal
devices. In addition, the operating environment of the devices may vary widely in temperature, supply
voltage, and noise. Usually delay analysis and simulation are performed at multiple corner conditions in
which combinations of best and worst device and environmental conditions are used. For circuits in
which the matching of individual transistors is required for correct operation such as current and voltage
reference circuits and amplifiers, despite care being taken in the design and layout, mismatch does occur. 30
For timing chains, strobes, latches, and memories as well as the analog functions previously described,
Monte Carlo analysis as well as worst-case analysis is often used to ensure correct operation and ascertain
delays.
In the design of a high-frequency processor, performance gain can be made by minimizing the variation
where possible and then taking advantage of systematic variation and only guard banding for random
variations, variations which are time variant, and those for which the cost of taking advantage of the
systematic variation exceeds the benefit. Methods of efficient models of the systematic and random
components for device and interconnect can be used by the designer to optimize the design and determine
what guard band is necessary to account for the random variations. 31,32
13.5 Summary
Designing for the increasingly difficult task of high-frequency processors is largely a process of optimizing
a design to within a reasonable distance of the constraints of (1) the ability of the interconnect to communicate
signals, distribute clocks, and supply power, (2) the current delivering capabilities and noise
margins of the devices, (3) the random or difficult to predict systematic variations in the processing, and
© 2002 by CRC Press LLC