U. Glaeser

Because synthesis tools do not support every language feature, models used for synthesis must use a
subset of the HDL’s features. In VHDL, signals should be used for synthesis models instead of variables.
HDL models intended for synthesis should not include propagation delay times. After logic synthesis,
actual delay times will be automatically calculated by the FPGA CAD tools for use in simulation. Initial
values for variables or signals are not supported in HDL synthesis tools. This means that most HDL
models originally written only for simulation use will not synthesize.
Using HDLs for Design Entry and Synthesis
To illustrate and compare the features of the two most widely used HDLs, VHDL and Verilog, two example
synthesis models will be examined. As seen in Table 12.1, VHDL and Verilog have a similar set of synthesis
operators with VHDL operators based on PASCAL and Verilog operators based on C. Some shift operators
are missing in Verilog, but they can be implemented in a single line of code with a few additional characters.
In VHDL processes, concurrent statements and entities execute in parallel. Inside a process, statements execute
in sequential order. In Verilog, modules and always blocks execute in parallel and statements inside an
always block execute sequentially just like processes in VHDL. Processes and always blocks have sensitivity
lists that specify when they should be reevaluated. Any signal that can change the output of a block must
be listed in the sensitivity list. VHDL processes and Verilog always blocks with a clock signal sensitivity
will generate flip-flops when synthesized.
© 2002 by CRC Press LLC
TABLE 12.1
HDL Operators Used for Synthesis
Synthesis Operation VHDL Operator Verilog Operator
Addition
+ +
Subtraction
− −
∗
Multiplication
∗ ∗
∗
Division
/ /
∗
Modulus
MOD %
∗
Remainder
REM
Concatenation—used to
combine bits
& { }
Logical shift left
∗∗
SLL
>
Arithmetic shift left
∗∗
SLA
Arithmetic shift right
∗∗
SRA
Rotate left
∗∗
ROL
Rotate right
∗∗
ROR
Equality
= ==
Inequality
/=
! =
Less than
< <
Less than or equal
Greater than or equal
>=
> =
Logical NOT NOT !
Logical AND AND &&
Logical OR OR ||
Bitwise NOT NOT ~
Bitwise AND AND &
Bitwise OR OR |
Bitwise XOR XOR ^
∗
Not supported in many HDL synthesis tools. In some synthesis
tools, only multiply and divide by powers of two (shifts) are supported.
Efficient implementation of multiply or divide hardware
frequently requires the user to specify the arithmetic algorithm and
design details in the HDL or call a FPGA vendor supplied function.
∗∗
Supported only in IEEE 1076–1993 VHDL.