U. Glaeser

Total Average Power
Putting together all the components of power dissipation, the total average power consumption of a logic
gate can be expressed as follows:
Ptotal = Pdynamic + Pdirect-path + Pstatic =
© 2002 by CRC Press LLC
(20.1)
Among these components, dynamic power is by far the most dominant component and accounts for
more than 80% of the total power consumption in modern day CMOS technology. Thus, the total average
power for all logic gates in the circuits can be approximated by summing up all the dynamic component
of each of the logic gate,
where n is the number of logic gates in the circuit.
Power Due to the Internal Nodes of a Logic Gate
The power consumption due to the internal nodes of the logic gates has been ignored in the above
analysis, which causes inaccuracy in the power consumption result. The internal node capacitances are
primarily due to the source and drain diffusion capacitances of the transistors, and are not as large as
the output node capacitance. Hence, total power consumption is still dominated by the charging and
discharging of the output node capacitances. Nevertheless, depending on the applied input vectors and
the sequence in which the input vectors are applied, the power consumption due to the internal nodes
of logic gates may contribute a significant portion of the total power consumption. Experimental results
in section 20.5 show that the power consumption due to the internal nodes can be as high as 20% of the
total power consumption for some circuits.
The impact of the internal nodes in the total power consumption is most significant when the internal
nodes are switching, but the output node remains unchanged, as shown in Fig. 20.4. The internal
capacitance, Cinternal,
is being charged, discharged, and recharged at time t0,
t1,
and t2,
respectively. During
this period of time, power is dissipated solely due to charging and discharging of the internal node.
FIGURE 20.4
P total
1
2
-- ⋅ Cload ⋅ Vsupply ⋅
2
1 2
-- ⋅ Vsupply ⋅
2
Charging and discharging of internal node.
B
=
n
∑
i=1
A B
A
2-input NAND
V dd
A+ Iavg ⋅ Vsupply + Ileakage ⋅ Vsupply C load i
⋅
A i
H = Logic High
Vout L = Logic Low
C-load
t0 , t2 t0 t1 t2 A : H L H
Vint B : L H L
V
C-int
out : H H H
Vint : H L H
t1