U. Glaeser

a fundamental property that distinguished the early DSP processors. On the TMS 320C1x, released in
the early ’80s, it took 2N cycles for a N tap filter (without the shift of the delay line) [5].
The modified Harvard architecture improves this idea even further. It is combined with a “repeat”
instruction and a specialized addressing mode, the circular addressing mode. In this case, one multiplyaccumulate
instruction is fetched from program memory and kept in the one instruction deep instruction
“cache.” Then the data access cycles are performed in parallel: the coefficient is fetched from the program
memory in parallel with the data sample being fetched from data memory. This architecture is found in
all early DSP processors and is the foundation for all following DSP architectures. The number of memory
accesses for one tap are reduced to two and these occur in the same cycle. Thus, one tap can execute in
one cycle and the multiply-accumulate unit is kept occupied every cycle.
Newer generation of DSP processors have even more memory banks, accompanying address generation
units and control hardware, such as the repeat instruction, to support multiple parallel accesses.
The execution of a 32-tap FIR filter on the dual Mac architecture of the Lucent DSP 1621, shown in
Fig. 42.56, will take only 19 cycles. The corresponding pseudo code is the following:
do 14 { //one instruction !
a0=a0+p0+p1
p0=xh*yh p1=xl*yl
y=*r0++ x=*pt0++
}
This code can be executed in 19 clock cycles with only 38 bytes of instruction code. The inner loop
takes one cycle to execute and as can be seen from the assembly code, seven operations are executed in
parallel: one addition, two multiplications, two memory reads, and two address pointer updates. Note
that the second pointer update, *pt0++, updates a circular address pointer.
Two architectures which speed up the FIR calculation to 0.5 cycle per tap are shown in Fig. 42.56. The
first one is the above mentioned Lucent DSP16210. The second one is an architecture presented in [9].
It has a multiply accumulate unit that operates at double the frequency from the memory accesses.
The difficult part in the implementation of this tight loop is the arrangement of the data samples in
memory. To supply the parallel Mac data paths, two 32-bit data items are read from memory and stored
in the X and Y register, as shown in Fig. 42.56. A similar split in lower and higher halfs occurs in the
FIGURE 42.56 DSP architectures for 0.5 cycle per FIR tap.
© 2002 by CRC Press LLC
16 x 16 mpy 16 x 16 mpy
AL ALUU
XDB(32)
IDB(32)
Y(32)
X(32)
p0 (32) p1 (32)
Shift/Sat. Shift/Sat.
ADD BM BMUU
ACC File
8 x 40
(a) Lucent DSP16210 architecture
1 MACHINE MEMORY X MEMORY Y
CYCLE
(MX)
(MY)
16-bit 16-bit 16-bit 16-bit
EVEN ODD EVEN ODD
SIDE SIDE SIDE SIDE
TEMP REG TEMP REG
16-bit
16-bit
A-BUS
B-BUS
16-bit 16-bit
1/2 MACHINE
CYCLE
1/2 MACHINE
CYCLE
POINTER X
(PX)
MULTIPLIER
32-bit
PIPELINE REG
ADDER
40-bit
ACC
BARREL SHIFTER
(b) MAC at double frequency [14]
POINTER Y
(PY)
MAC UNIT