U. Glaeser

Manchester carry chain (MCC) is one of the simplest schemes for RCA that utilizes MOS technology
[8,9]. The carry chain is constructed of series-connected pass transistors whose gates are controlled by
the carry-propagate signal p i at every bit position i of n 1-bit FAs. This scheme can offer simple hardware
implementation with less power as compared with other elaborate schemes. Because of distortion due
to RC time constant, the carry signal needs to be regenerated by inserting inverters or true buffers at
appropriate locations in the carry chain. Though this compensation needs additional transistors, the
total power may be reduced appreciably if buffers are equipped with efficiently.
Carry Skip Adder
If the carry-propagate signals pi that belong to the bit positions from the mth to (m + k)th are all 1, the carry
signal at the (m − 1)th bit position can bypass through (k + 1) bits to the (m + k)th bit position without
rippling through these bits. A carry skip adder (CSKA) is a scheme to utilize this principle for shortening the
longest path of the carry propagation. A fixed-group CSKA is such that the n 1-bit FAs to construct an n-bit
adder is divided equally into k groups over which the carry signal can bypass if the condition to skip is fulfilled.
The maximum delay of the carry propagation is reduced to a factor of 1/k as compared with RCA [1].
MCC is often used with several bypass circuits to speed up the carry propagation in longer word
addition [10]. Figure 9.22(a) is a case of such implementation. Though this 4-bit bypass circuit may be
considered to work well at a glance, it is not true because of the signal conflict during the transient phase
from the former state to the new state to settle to, as shown in Fig. 9.22(c) with transition of the node
voltage Vs(A) at the node A in Fig. 9.22(a) [11]. To avoid this unexpected transition delay, it is necessary
to cut off all of other signal paths than expected logically as shown in Fig. 9.22(b). Under this modified
scheme [11], the bypass circuit can function as expected like shown in Fig. 9.22(c), with change of the
node voltage Vs(B) at the node B in Fig. 9.22(b).
A variable block adder (VBA) allows the groups to be different in size [12], so that the maximum
delay is further reduced from the fixed group CSKA. The number of adders in a group is gradually
increased from LSB toward the middle bit position, and then reduced toward MSB. This scheme may
lead us to the total delay dependency on the carry propagation in the order of square root of n. Extension
of this approach to multiple levels of carry skip is possible for further speeding up on a fast adder.
Carry Lookahead Adder
A carry lookahead adder (CLA) [13] utilizes fully two types of signals pi and gi at the ith bit position of
an n-bit adder to control carry propagation. For instance, the carry signals ci, ci+1, and ci+2 can be estimated
c i-1 c i+3
gi
pi
FIGURE 9.22(a) Carry skip circuit that causes conflict during signal transient.
© 2002 by CRC Press LLC
pi
pi+1
pi+2
pi+3
g
p
i+1
i+1
~g
p
i+2
i+2
~g
p
i+3
i+3
node A