U. Glaeser

The principle of register renaming is straightforward. The processor removes false data dependencies
by writing the results of the instructions first into dynamically allocated rename buffers, rather than into
the specified destination registers. For instance, in the case of the following WAR dependency
the processor renames the destination register of i
2
i
2
becomes
© 2002 by CRC Press LLC
i1:
add …, r2,
…; [… ← (r2)
+ (…)]
i2:
mul r2,
…, …; [r2
← (…) ∗ (…)]
(r2),
say to r33.
Then after the renaming of r2,
instruction
: mul r33,
…, …; [33 ← (…) ∗ (…)]
and the processor writes the result of i′ 2 into r33
instead of into r2.
This resolves the previous WAR
dependency between i1
and i2.
In subsequent instructions, however, references to the source register r2
must be redirected to the rename buffer r33
as long as the renaming remains valid. In the next section
we give a detailed description of the whole rename process.
4
A precursor to register renaming was introduced in 1967 by Tomasulo in the IBM 360/91, a scalar
supercomputer of that time, which pioneered both pipelining and shelving. The 360/91 renamed floating
point registers in order to preserve the logical consistency of the program execution, rather than to
increase processor performance by removing false data dependencies.
5
Tjaden and Flynn were the first to suggest the use of register renaming for removing false data dependencies.
They proposed the renaming of load type instructions, but they did not yet use the term “ register
6
renaming.”
This specific term was introduced a few years later, in 1975, by Keller who extended renaming
to cover all instructions including a destination register. He also described a possible hardware implementation
of this technique. Because of the complexity of its implementation, however, about two decades
passed until register renaming came into widespread use in superscalars in the beginning of the 1990s.
Early superscalar models of significant processor lines, such as the PA 7100, SuperSparc, Alpha 21064,
R8000, and the Pentium, typically did not yet use renaming as indicated in Fig. 6.1. Renaming appeared
gradually, first in a restricted form, called partial renaming, in the beginning of the 1990s, in the IBM
RS/6000 (Power1), Power2, PowerPC 601, and in NextGen’s Nx586 processors, as depicted in Fig. 6.1.
Partial renaming restricts renaming to one or to a few data types, such as floating point loads or floating
point instructions, as detailed in the section “Scope of Register Renaming.” Full renaming emerged later,
beginning in 1992, first in the high-end models of the IBM mainframe family ES/9000, then in the
PowerPC 603. Subsequently, renaming spread into virtually all superscalar processors with the notable
exception of Sun’s UltraSparc line. At present register renaming is considered to be a standard feature of
performance oriented superscalar processors.
Overview of the Rename Process
i 2 ′
The rename process itself is considerably complex. It consists of a number of rename specific tasks—such
as renaming the destination and the source registers, fetching renamed source operands, updating the
rename buffers, releasing allocated rename buffers, recovery of the rename process from faultily executed
speculative execution, etc. In addition, each of the rename specific tasks may be implemented in a number
of different ways. Furthermore, the kind of the underlying microarchitecture affects how the rename
process is carried out. Therefore, each concrete description of the rename process is related to a particular
kind of the renaming technique employed and the underlying microarchitecture. Thus, before describing
the rename process we need to be specific about both the renaming technique and the microarchitecture
assumed.
As far as the renaming technique is concerned, in a subsequent section, we will show that eight basic
alternatives for renaming are available. In our description of the rename process, we need to presume one