U. Glaeser

FIGURE 31.15 Receiver design using clocked amplifier/sampler as first stage.
level-shifted 12 to accommodate the clocked comparator that follows [34]. A high clock level resets the
comparator shown in Fig. 31.14. The negative clock edge samples the data and starts a positive feedback
that regeneratively amplifies the sampled value to digital values during the low clock phase. To demultiplex
the data, the comparators operate on different clock phases. The amplification is exponentially dependent
on the duration of the low phase. Because the comparator has high gain, the first stage does not need
significant gain. Some gain reduces the effective input offset voltage since the contribution of the comparator’s
offset is divided by the gain. Mismatch in the feedback devices and clock coupling of the comparators
can introduce significant offsets. For very high data rates, the drawback of the design is that the first
stage must have sufficient bandwidth to minimize ISI. Furthermore, delay variation of the first stage can
add timing noise.
A simple design can avoid ISI by eliminating the first stage and sampling/demultiplexing the input with
comparators directly [24,52]. Because the comparators are reset before each sample, no signal energy from
previous bits remains hence removing ISI; however, direct sampling is noisier and has larger static offsets.
Figure 31.15 illustrates an alternate design that clocks the first stage to remove ISI but still conditions the
signal [26,43]. During the low phase of the clock, the amplifier output is reset. During the high phase
of the clock, the amplifier conditions the data. For demultiplexing, two clocked amplifiers loads the input.
A comparator samples the amplifier output to further amplify to digital levels. The clock used for the clocked
amplifier must be timed with the arriving signal to amplify the proper bit. The timing issue will be discussed
in section 31.4.
dc Offsets
Random dc offsets limit the voltage resolution of the receiver. These offset are due to random mismatches
in the devices and scales inversely with the size of the device [35]. Because minimum size devices are often
used to minimize pin capacitance and power dissipation, input-referred offset of amplifiers and comparators
can be tens of millivolts.
To compensate for the error, devices are added that can create an offset in either the first amplifier or
the comparator. The control can be open-loop where the compensation value is determined with an
initial calibration [10]. Figure 31.16(a) shows a comparator with digitally controllable switches that
differentially inject an error current. The open-loop compensation is commonly digital so the value does
not drift in time. Alternatively, the control can be continuously operating and closed-loop [51]. As shown
in Figure 31.16(b), a third nonoverlapping clock phase, clk 1, is added to the reset and amplify (clk 0) phases
of operation. Clk 1 reconfigures the amplifier to short the inputs and to store the value of the offset on
12 The input common-mode voltage depends on the transmitter and the I/O specification.
© 2002 by CRC Press LLC
V i+
clocked amplifier 0 o
clk
bias
clk
Vo Vo ref
clocked amplifier 180 o