U. Glaeser

James O. Hamblen
Georgia Institute of Technology
12.1 Programmable Logic Technology
© 2002 by CRC Press LLC
12
FPGAs for Rapid
Prototyping
12.1 Programmable Logic Technology
PALs, PLAs, CPLDs, FPGAs, ASICs, and Full Custom VLSI
Devices • Applications of FPGAs • Product Term
(EEPROM and Fuse-Based) Devices • Lookup Table
(SRAM-Based) Devices • Architecture of Newer
Generation FPGAs
12.2 CAD Tools for Rapid Prototyping Using FPGAs
Design Entry • Using HDLs for Design Entry and
Synthesis • IP cores for FPGAs • Logic Simulation
and Test • FPGA Place and Route Tools • Device
Programming and Hardware Verification
Digital systems can be implemented using several hardware technologies. As shown in Fig. 12.1, field
programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), and application
specific integrated circuits (ASICs), are integrated circuits whose internal functional operation is defined
by the user. ASICs require a final customized manufacturing step for the user-defined function. Programmable
logic devices such as CPLDs or FPGAs require user configuration or programming to implement
the desired function. Full custom VLSI devices are internally hardwired and optimized to perform
a fixed function. Examples of full custom very large scale integrated (VLSI) devices include the microprocessor
and RAM chips used in computers.
PALs, PLAs, CPLDs, FPGAs, ASICs, and Full Custom VLSI Devices
The different device technologies each have a different set of design tradeoffs as seen in Fig. 12.2. The
design of a full custom VLSI device at the transistor level requires several years of engineering effort for
design, testing, and fabrication [1,2]. This expensive development effort is only economical for the highest
volume devices. Full custom VLSI devices will produce the highest performance, but they also have the
highest development cost and the longest time to market.
ASICs are typically divided into two categories, gate arrays and standard cells. Gate arrays are built
from arrays of pre-manufactured logic cells. A single logic cell implements only a few gates or a flip-flop.
A final custom manufacturing step is required to interconnect the sea of logic cells on a gate array. This
interconnection pattern is created by the user to implement a particular design. Standard cell devices
contain no fixed internal structure. For standard cell devices, the device manufacturer creates a custom
photographic mask to build the chip based on the user’s selection of devices. These devices typically
include communications and bus controllers, ALUs, RAM, ROM, and microprocessors from the manufacturer’s
standard cell library.