U. Glaeser

FIGURE 10.79 Static noise margin of the memory cell.
provide sufficient current to flip the cell and latch the new data. Since access transistor is a single N-pass
transistor, the bit line (Bit or Bit#), which is a logic “0”, is most effective in the write (and read) operation.
Inside the cell the logic “1” must be restore by the P-transistors. During read, Bit and Bit# are first precharged
to “1” then the LWL is activated again for the selected row. Depending on the data stored in the
cell, ND1 (or ND2) will pull the bit line down. The read operation must not destroy the stored data.
The NP transistor must be sized correctly with respect to driving ND transistor and restoring P-transistor.
During the write a logic “0” on the bit line must be able to flip the cell. This means that NP transistor
must be large enough to overcome the P-transistor. This transistor must also be large enough to decay
the bit line for a fast read time; however, its size with respect to driver transistor ND1 (ND2) must be
small enough such that during a read the internal node holding a “0” does not rise sufficiently to flip
the cell. Other considerations, like sub-threshold leakage and glitches during a LWL transition, suggest
to keep this transistor small.
The ND transistor drives the bit line down during a read. Since the bit line capacitance is high, for
high-speed read this transistor must be large. Also it must be large enough to maintain the logic “0” in
the cell while pulling down the pre-charged bit line during a read. However, to have some write margin
this transistor must not be too large. When writing a “0” to one side of the memory cell (for example, S1), the ND2 transistor is fighting to maintain the old value. A large ND size requires the bit line to be pulled
too close to Vss. This limits the write margin. A large ND size also increases the standby current of the
memory.
The restoring P-transistor pull up the high side of the cell to a logic “1” and maintain it at that level.
Since the P-transistor only drives the internal cell nodes, it could be small. Smaller P-transistor also
reduces the sub-threshold current. However, the P-transistor must be large enough to quickly restore a
partially logic “1” written through N-pass transistor to a full level. Otherwise a read immediately following
a write may not meet the access time. The P-transistor must also be large enough to reduce soft error rate.
These conflicting requirements on the absolute and relative size of transistors in the cell are summarized
in a graphical analysis of the transfer curve of the memory latch, Fig. 10.79. To set up this graph, normalized
transfer function of the inverter in the cell is overlapped with its mirror curve. The maximum square that
fits these two characteristics defines the noise margin for read and write. This square is also an indication
of the cell stability. This graph must be analyzed across the voltage, temperature, and process variations.
In the next section some guidelines are given for these simulations.
Memory Cell Stability and Noise Margin Analysis
Some parameters of a transistor are subject to variations during fabrication. These variations can be
lumped and modeled in the transistor length and threshold. Figure 10.80(a) shows an ideal transistor
that has a width of W and length L. In a typical process, the transistor threshold voltage is Vt. A weak
transistor is modeled by increasing the L and threshold by ∆L and ∆Vt, respectively. ∆Vt must be
represented by a correct battery polarity in the schematic. A strong transistor is modeled by decreasing
the L and threshold by ∆L and ∆Vt. © 2002 by CRC Press LLC
V s2
V dd
1
0.5
0.5
V F
1
V s1
V dd