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U. Glaeser

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FIGURE 2.50 Diffusion-area sharing for better layout.<br />

FIGURE 2.51 Comparison of pass-transistor circuit and CMOS circuit for 2-input NAND/NOR logic.<br />

CMOS circuit provides better performance in terms of area and delay. However, a PTL circuit still provides<br />

lower power consumption because of its pMOS-free structure, which enables small capacitance.<br />

Pass-transistor circuits are more suitable for implementing logic functions in which some signals are<br />

selected by other signals. In contrast, CMOS circuits are more suitable for implementing NAND/NOR<br />

logic (or AND/OR logic). Thus, PTL and CMOS mixed structures, in which logic corresponding to a<br />

selector is implemented with PTL circuits and other logic is implemented with CMOS circuits, are<br />

attractive [33,34]. In this section, such mixed-logic circuits called pass-transistor and CMOS collaborated<br />

logic (PCCL) are described.<br />

The key to PCCL is finding CMOS-beneficial parts and selector-beneficial parts in the logic functions.<br />

To accomplish this, the BDD-based method shown in Fig. 2.52(a) is used, in which first an entire PTL<br />

circuit is constructed from a multilevel BDD or decomposed BDD, and then some parts are replaced<br />

with CMOS circuits. The key to this procedure is to find CMOS-beneficial functions based on the BDD.<br />

This is accomplished as follows: those selectors with one of two inputs fixed to V dd or Gnd operate as<br />

AND or OR logic (NAND or NOR logic) rather than as a selector, so they are good candidates to be replaced<br />

with CMOS circuits, as shown in Fig. 2.52(b). Using this method, logic functions can be categorized into<br />

pro-selector functions and pro-AND/OR functions.<br />

Figure 2.53 shows a detailed example of the PCCL synthesis flow. For the logic function shown in<br />

Fig. 2.53(a), the multilevel BDD shown in Fig. 2.53(b) is constructed. The PTL shown in Fig. 2.53(c) is<br />

then obtained from the BDD. Then, in the synthesized PTL, selectors in which one of the two data inputs<br />

is fixed to V dd or Gnd are searched for. As described before, however, because of the low-power characteristics<br />

of the pass-transistor circuits, the power consumption will increase if all these pass-transistor<br />

© 2002 by CRC Press LLC<br />

A<br />

Eulerian path<br />

P4<br />

C<br />

P3<br />

B<br />

C<br />

A<br />

P2<br />

P1<br />

B<br />

A A B<br />

P3 P4<br />

(a) Circuit (b) Layout<br />

B<br />

D G S S G D D G S S D G<br />

P1<br />

P2 Diffusion-area

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