U. Glaeser

Tadahiro Kuroda
Keio University
© 2002 by CRC Press LLC
3
High-Speed, Low-Power
Emitter Coupled
Logic Circuits
3.1 Active Pull-Down ECL Circuits
3.2 Low-Voltage ECL Circuits
Emitter-coupled logic (ECL) circuits have often been employed in very high-speed VLSI circuits. However,
a passive pull-down scheme in an output stage results in high power dissipation as well as slow pulldown
transition. Gate stacking in a current switch logic stage keeps ECL circuits from operating at low
power supply voltages. In this section, a high-speed active pull-down scheme in the output stage, as well
as a low-voltage series-gating scheme in the logic stage will be presented. The two circuit techniques can
be employed together to obtain multiple effects in terms of speed and power.
3.1 Active Pull-Down ECL Circuits
An ECL inverter circuit is depicted in Fig. 3.1, together with the simulated output voltage and pull-down
current waveforms. As shown in the figure, the pull-down transition time increases much more rapidly
than the pull-up transition time as the load capacitance increases. This slow pull-down transition time,
and consequently unbalanced pull-up and pull-down switching speed, can cause an erroneous operation
of the circuit due to signal skew or because of a racing condition.
The figure also demonstrates the disadvantageous power consumption of the circuit. The circuit
requires a constant pull-down current I EF. This power is consumed even when the gate output is not being
switched. To reduce this power loss, the current I EF must be reduced. However, reducing the current I EF
causes the pull-down transition time to increase to an unacceptable level. This high power dissipation
and slow pull-down transition of ECL circuits has long been known to limit their VLSI applications. The
power-speed limitation comes primarily from the passive pull-down scheme in the emitter-follower stage.
Various active pull-down schemes have been proposed [1–5] where a capacitor is utilized to couple a
transient voltage pulse to the base of a pull-down npn transistor. An ac-coupled active-pull-down ECL
(AC-APD-ECL) circuit [3] is depicted in Fig. 3.2. The steady-state dc current can be kept an order of
magnitude lower than in the conventional ECL gate. As for the transient action, C X and R B determine the
magnitude of the transient collector current of transistor QD. C E and R E determine the time while
transistor QD turns on. These capacitors and resistors should be optimized for a specific loading condition,
since they determine the dynamic pull-down current. The dynamic pull-down current is predetermined
for a given design. In other words, there is a finite range of loading, outside of which proper operation of
the circuit cannot be ensured.